[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Duncan Laurie (Code Review)
gerrit at coreboot.org
Mon Mar 26 11:47:03 CEST 2018
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25365
Change subject: soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
......................................................................
soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/chell/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
15 files changed, 16 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25365/1
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index f8c3054..2f07753 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -36,7 +36,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 2e62f41..f24d5c9 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -32,7 +32,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index a9646ec..9d120ea 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -67,7 +67,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 0dff3d9..94d9e53 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -36,7 +36,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 074e8a2..032c426 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -38,7 +38,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 0b3387e..a04dd95 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -34,7 +34,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 6946b38..8a94682 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -38,7 +38,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 65955eb..2688d58 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -38,7 +38,6 @@
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 7903ddc..6da73dc 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -170,7 +170,6 @@
# USB related
register "SsicPortEnable" = "1"
- register "XdciEnable" = "0"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 1fc19a5..b7fff8a 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -41,7 +41,6 @@
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index 647f054..fbc6942 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -41,7 +41,6 @@
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index aac4a8f..f3719a5 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -84,6 +84,7 @@
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index f60c08d..0c1dfa6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -78,7 +79,7 @@
/* UPD parameters to be initialized before SiliconInit */
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
int i;
@@ -140,7 +141,6 @@
params->EnableAzalia = config->EnableAzalia;
params->IoBufferOwnership = config->IoBufferOwnership;
params->DspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->EnableSata = config->EnableSata;
params->SataMode = config->SataMode;
@@ -196,6 +196,12 @@
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
params->SendVrMbxCmd = config->SendVrMbxCmd;
/* Acoustic Noise Mitigation */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b77f6dc..dc79869 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -237,7 +237,6 @@
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
- u8 XdciEnable;
u8 SsicPortEnable;
/* SMBus */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3bc66b2..b4fed26 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@@ -221,7 +222,6 @@
params->PchHdaEnable = config->EnableAzalia;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
@@ -284,6 +284,12 @@
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
/*
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3c84beac87452f17490de32082030880834501d
Gerrit-Change-Number: 25365
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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