<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25365">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Limit xDCI feature when VBOOT is enabled<br><br>Use the common xDCI function to check if the controller is allowed<br>in the current mode before enabling it.  Otherwise, disable the<br>PCI device if it has been enabled in devicetree.<br><br>To make the SOC behavior consistent the XdciEnable config option<br>is removed in favor of direct control by devicetree.cb and the<br>mainboards that had defined it were adjusted accordingly.<br><br>This was tested on an Eve board with xDCI enabled in devicetree.cb<br>to ensure the xDCI device is enabled in developer mode and disabled<br>in normal mode.<br><br>Change-Id: Ic3c84beac87452f17490de32082030880834501d<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/mainboard/google/chell/devicetree.cb<br>M src/mainboard/google/eve/devicetree.cb<br>M src/mainboard/google/fizz/devicetree.cb<br>M src/mainboard/google/glados/devicetree.cb<br>M src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>M src/mainboard/google/poppy/variants/nami/devicetree.cb<br>M src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>M src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>M src/mainboard/intel/saddlebrook/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>15 files changed, 16 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25365/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb</span><br><span>index f8c3054..2f07753 100644</span><br><span>--- a/src/mainboard/google/chell/devicetree.cb</span><br><span>+++ b/src/mainboard/google/chell/devicetree.cb</span><br><span>@@ -36,7 +36,6 @@</span><br><span>       register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb</span><br><span>index 2e62f41..f24d5c9 100644</span><br><span>--- a/src/mainboard/google/eve/devicetree.cb</span><br><span>+++ b/src/mainboard/google/eve/devicetree.cb</span><br><span>@@ -32,7 +32,6 @@</span><br><span>     register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb</span><br><span>index a9646ec..9d120ea 100644</span><br><span>--- a/src/mainboard/google/fizz/devicetree.cb</span><br><span>+++ b/src/mainboard/google/fizz/devicetree.cb</span><br><span>@@ -67,7 +67,6 @@</span><br><span>         register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb</span><br><span>index 0dff3d9..94d9e53 100644</span><br><span>--- a/src/mainboard/google/glados/devicetree.cb</span><br><span>+++ b/src/mainboard/google/glados/devicetree.cb</span><br><span>@@ -36,7 +36,6 @@</span><br><span>         register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>index 074e8a2..032c426 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb</span><br><span>@@ -38,7 +38,6 @@</span><br><span>         register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "1"</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>index 0b3387e..a04dd95 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb</span><br><span>@@ -34,7 +34,6 @@</span><br><span>     register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>index 6946b38..8a94682 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb</span><br><span>@@ -38,7 +38,6 @@</span><br><span>     register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "1"</span><br><span>diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>index 65955eb..2688d58 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb</span><br><span>@@ -38,7 +38,6 @@</span><br><span>     register "DspEnable" = "1"</span><br><span>       register "IoBufferOwnership" = "3"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "1"</span><br><span>diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>index 7903ddc..6da73dc 100644</span><br><span>--- a/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/saddlebrook/devicetree.cb</span><br><span>@@ -170,7 +170,6 @@</span><br><span> </span><br><span>   # USB related</span><br><span>        register "SsicPortEnable" = "1"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span> </span><br><span>  register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"  # OTG</span><br><span>       register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"  # Touch Pad</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>index 1fc19a5..b7fff8a 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>@@ -41,7 +41,6 @@</span><br><span>        register "DspEnable" = "0"</span><br><span>       register "IoBufferOwnership" = "0"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>index 647f054..fbc6942 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>@@ -41,7 +41,6 @@</span><br><span>         register "DspEnable" = "0"</span><br><span>       register "IoBufferOwnership" = "0"</span><br><span>       register "EnableTraceHub" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">-     register "XdciEnable" = "0"</span><br><span>      register "SsicPortEnable" = "0"</span><br><span>  register "SmbusEnable" = "1"</span><br><span>     register "Cio2Enable" = "0"</span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index aac4a8f..f3719a5 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -84,6 +84,7 @@</span><br><span>         select SOC_INTEL_COMMON_BLOCK_SPI</span><br><span>    select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span>  select SOC_INTEL_COMMON_BLOCK_UART</span><br><span style="color: hsl(120, 100%, 40%);">+    select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span>   select SOC_INTEL_COMMON_BLOCK_XHCI</span><br><span>   select SOC_INTEL_COMMON_GFX_OPREGION</span><br><span>         select SOC_INTEL_COMMON_NHLT</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index f60c08d..0c1dfa6 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span> #include <soc/acpi.h></span><br><span> #include <soc/interrupt.h></span><br><span> #include <soc/irq.h></span><br><span>@@ -78,7 +79,7 @@</span><br><span> /* UPD parameters to be initialized before SiliconInit */</span><br><span> void soc_silicon_init_params(SILICON_INIT_UPD *params)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);</span><br><span>        const struct soc_intel_skylake_config *config = dev->chip_info;</span><br><span>   int i;</span><br><span> </span><br><span>@@ -140,7 +141,6 @@</span><br><span>     params->EnableAzalia = config->EnableAzalia;</span><br><span>   params->IoBufferOwnership = config->IoBufferOwnership;</span><br><span>         params->DspEnable = config->DspEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-    params->XdciEnable = config->XdciEnable;</span><br><span>       params->Device4Enable = config->Device4Enable;</span><br><span>         params->EnableSata = config->EnableSata;</span><br><span>       params->SataMode = config->SataMode;</span><br><span>@@ -196,6 +196,12 @@</span><br><span>    dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span>       params->ShowSpiController = dev->enabled;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(120, 100%, 40%);">+     dev = dev_find_slot(0, PCH_DEVFN_USBOTG);</span><br><span style="color: hsl(120, 100%, 40%);">+     if (!xdci_can_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+               dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+  params->XdciEnable = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   params->SendVrMbxCmd = config->SendVrMbxCmd;</span><br><span> </span><br><span>       /* Acoustic Noise Mitigation */</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index b77f6dc..dc79869 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -237,7 +237,6 @@</span><br><span>   /* USB related */</span><br><span>    struct usb2_port_config usb2_ports[16];</span><br><span>      struct usb3_port_config usb3_ports[10];</span><br><span style="color: hsl(0, 100%, 40%);">- u8 XdciEnable;</span><br><span>       u8 SsicPortEnable;</span><br><span> </span><br><span>       /* SMBus */</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 3bc66b2..b4fed26 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -26,6 +26,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/acpi.h></span><br><span> #include <soc/intel/common/vbt.h></span><br><span>@@ -221,7 +222,6 @@</span><br><span>       params->PchHdaEnable = config->EnableAzalia;</span><br><span>   params->PchHdaIoBufferOwnership = config->IoBufferOwnership;</span><br><span>   params->PchHdaDspEnable = config->DspEnable;</span><br><span style="color: hsl(0, 100%, 40%);">-      params->XdciEnable = config->XdciEnable;</span><br><span>       params->Device4Enable = config->Device4Enable;</span><br><span>         params->SataEnable = config->EnableSata;</span><br><span>       params->SataMode = config->SataMode;</span><br><span>@@ -284,6 +284,12 @@</span><br><span>    dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span>       params->ShowSpiController = dev->enabled;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(120, 100%, 40%);">+     dev = dev_find_slot(0, PCH_DEVFN_USBOTG);</span><br><span style="color: hsl(120, 100%, 40%);">+     if (!xdci_can_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+               dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+  params->XdciEnable = dev->enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   /*</span><br><span>    * Send VR specific mailbox commands:</span><br><span>         * 000b - no VR specific command sent</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25365">change 25365</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25365"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic3c84beac87452f17490de32082030880834501d </div>
<div style="display:none"> Gerrit-Change-Number: 25365 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>