[coreboot-gerrit] Change in coreboot[master]: fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD Headers
Kin Wai Ng (Code Review)
gerrit at coreboot.org
Fri Mar 23 07:58:51 CET 2018
Kin Wai Ng has uploaded this change for review. ( https://review.coreboot.org/25335
Change subject: fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD Headers
......................................................................
fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD Headers
Header files based on FSP 7.0.25.34
BUG=none
BRANCH=none
TEST=built coreboot without build error.
Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h
A src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
6 files changed, 6,586 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/25335/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..fca01e9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
@@ -0,0 +1,67 @@
+/** @file
+ Header file for Firmware Version Information
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
new file mode 100644
index 0000000..ae25814
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
new file mode 100644
index 0000000..a147f4f
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
@@ -0,0 +1,2804 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT32 MemorySpdPtr00;
+
+/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT32 MemorySpdPtr01;
+
+/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT32 MemorySpdPtr10;
+
+/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT32 MemorySpdPtr11;
+
+/** Offset 0x0058 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x005A - Dq Byte Map CH0
+ Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqByteMapCh0[12];
+
+/** Offset 0x0066 - Dq Byte Map CH1
+ Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqByteMapCh1[12];
+
+/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqsMapCpu2DramCh0[8];
+
+/** Offset 0x007A - Dqs Map CPU to DRAM CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqsMapCpu2DramCh1[8];
+
+/** Offset 0x0082 - RcompResister settings
+ Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design
+ Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide
+ the appropriate values.
+**/
+ UINT16 RcompResistor[3];
+
+/** Offset 0x0088 - RcompTarget settings
+ RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,
+ otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x0092 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x0093 - VREF_CA
+ CA Vref routing: board-dependent
+ 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
+ 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
+**/
+ UINT8 CaVrefConfig;
+
+/** Offset 0x0094 - Smram Mask
+ The SMM Regions AB-SEG and/or H-SEG reserved
+ 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+ UINT8 SmramMask;
+
+/** Offset 0x0095 - MRC Fast Boot
+ Enables/Disable the MRC fast path thru the MRC
+ $EN_DIS
+**/
+ UINT8 MrcFastBoot;
+
+/** Offset 0x0096 - Rank Margin Tool per Task
+ This option enables the user to execute Rank Margin Tool per major training step
+ in the MRC.
+ $EN_DIS
+**/
+ UINT8 RmtPerTask;
+
+/** Offset 0x0097 - Training Trace
+ This option enables the trained state tracing feature in MRC. This feature will
+ print out the key training parameters state across major training steps.
+ $EN_DIS
+**/
+ UINT8 TrainTrace;
+
+/** Offset 0x0098 - Intel Enhanced Debug
+ Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
+ 0 : Disable, 0x400000 : Enable
+**/
+ UINT32 IedSize;
+
+/** Offset 0x009C - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x00A0 - MMIO Size
+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+ UINT16 MmioSize;
+
+/** Offset 0x00A2 - Probeless Trace
+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+ This also requires IED to be enabled.
+ $EN_DIS
+**/
+ UINT8 ProbelessTrace;
+
+/** Offset 0x00A3 - GDXC IOT SIZE
+ Size of IOT and MOT is in 8 MB chunks
+**/
+ UINT8 GdxcIotSize;
+
+/** Offset 0x00A4 - GDXC MOT SIZE
+ Size of IOT and MOT is in 8 MB chunks
+**/
+ UINT8 GdxcMotSize;
+
+/** Offset 0x00A5 - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x00A6 - Spd Address Tabl
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[4];
+
+/** Offset 0x00AA - Platform Debug Consent
+ To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
+ Enabling this BIOS option may alter the default value of other debug-related BIOS
+ options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
+ have the same setting
+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
+**/
+ UINT8 PlatformDebugConsent;
+
+/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
+ This BIOS option enables kernel and platform debug for USB3 interface over a UFP
+ Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DciUsb3TypecUfpDbg;
+
+/** Offset 0x00AC - PCH Trace Hub Mode
+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
+ 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
+**/
+ UINT8 PchTraceHubMode;
+
+/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size
+ Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg0Size;
+
+/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size
+ Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg1Size;
+
+/** Offset 0x00AF - PchPreMemRsvd
+ Reserved for PCH Pre-Mem Reserved
+ $EN_DIS
+**/
+ UINT8 PchPreMemRsvd[9];
+
+/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x00B9 - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGfx;
+
+/** Offset 0x00BA - Aperture Size
+ Select the Aperture Size.
+ 0:128 MB, 1:256 MB, 2:512 MB
+**/
+ UINT8 ApertureSize;
+
+/** Offset 0x00BB - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x00BC - SA GV
+ System Agent dynamic frequency support and when enabled memory will be training
+ at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
+ 2=FixedHigh, and 3=Enabled.
+ 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x00BD
+**/
+ UINT8 UnusedUpdSpace0;
+
+/** Offset 0x00BE - DDR Frequency Limit
+ Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
+ i.e. divide by 133 or 100
+ 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
+ 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto
+**/
+ UINT16 DdrFreqLimit;
+
+/** Offset 0x00C0 - Low Frequency
+ SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
+ 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 FreqSaGvLow;
+
+/** Offset 0x00C2 - Mid Frequency
+ SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
+ 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 FreqSaGvMid;
+
+/** Offset 0x00C4 - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x00C5 - Channel A DIMM Control
+ Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmChannel0;
+
+/** Offset 0x00C6 - Channel B DIMM Control
+ Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmChannel1;
+
+/** Offset 0x00C7 - Scrambler Support
+ This option enables data scrambling in memory.
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x00C8
+**/
+ UINT8 UnusedUpdSpace1[16];
+
+/** Offset 0x00D8 - SPD Profile Selected
+ Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
+ Profile 1, 3=XMP Profile 2
+ 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
+**/
+ UINT8 SpdProfileSelected;
+
+/** Offset 0x00D9 - Memory Reference Clock
+ 100MHz, 133MHz.
+ 0:133MHz, 1:100MHz
+**/
+ UINT8 RefClk;
+
+/** Offset 0x00DA - Memory Voltage
+ Memory Voltage Override (Vddq). Default = no override
+ 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+ Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+ UINT16 VddVoltage;
+
+/** Offset 0x00DC - Memory Ratio
+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+ recalculate memory timings listed below.
+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 Ratio;
+
+/** Offset 0x00DD - QCLK Odd Ratio
+ Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
+ $EN_DIS
+**/
+ UINT8 OddRatioMode;
+
+/** Offset 0x00DE - tCL
+ CAS Latency, 0: AUTO, max: 31
+**/
+ UINT8 tCL;
+
+/** Offset 0x00DF - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 34
+**/
+ UINT8 tCWL;
+
+/** Offset 0x00E0 - tRCD/tRP
+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
+**/
+ UINT8 tRCDtRP;
+
+/** Offset 0x00E1 - tRRD
+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
+**/
+ UINT8 tRRD;
+
+/** Offset 0x00E2 - tFAW
+ Min Four Activate Window Delay Time, 0: AUTO, max: 63
+**/
+ UINT16 tFAW;
+
+/** Offset 0x00E4 - tRAS
+ RAS Active Time, 0: AUTO, max: 64
+**/
+ UINT16 tRAS;
+
+/** Offset 0x00E6 - tREFI
+ Refresh Interval, 0: AUTO, max: 65535
+**/
+ UINT16 tREFI;
+
+/** Offset 0x00E8 - tRFC
+ Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
+**/
+ UINT16 tRFC;
+
+/** Offset 0x00EA - tRTP
+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
+ values: 5, 6, 7, 8, 9, 10, 12
+**/
+ UINT8 tRTP;
+
+/** Offset 0x00EB - tWR
+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+ 20, 24, 30, 34, 40
+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+ 34:34, 40:40
+**/
+ UINT8 tWR;
+
+/** Offset 0x00EC - tWTR
+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
+**/
+ UINT8 tWTR;
+
+/** Offset 0x00ED - NMode
+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+ UINT8 NModeSupport;
+
+/** Offset 0x00EE - DllBwEn[0]
+ DllBwEn[0], for 1067 (0..7)
+**/
+ UINT8 DllBwEn0;
+
+/** Offset 0x00EF - DllBwEn[1]
+ DllBwEn[1], for 1333 (0..7)
+**/
+ UINT8 DllBwEn1;
+
+/** Offset 0x00F0 - DllBwEn[2]
+ DllBwEn[2], for 1600 (0..7)
+**/
+ UINT8 DllBwEn2;
+
+/** Offset 0x00F1 - DllBwEn[3]
+ DllBwEn[3], for 1867 and up (0..7)
+**/
+ UINT8 DllBwEn3;
+
+/** Offset 0x00F2 - ISVT IO Port Address
+ ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
+**/
+ UINT8 IsvtIoPort;
+
+/** Offset 0x00F3 - CPU Trace Hub Mode
+ Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
+ trace hub functionality.
+ 0: Disable, 1:Target Debugger Mode
+**/
+ UINT8 CpuTraceHubMode;
+
+/** Offset 0x00F4 - CPU Trace Hub Memory Region 0
+ CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg0Size;
+
+/** Offset 0x00F5 - CPU Trace Hub Memory Region 1
+ CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg1Size;
+
+/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
+ Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PeciC10Reset;
+
+/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command
+ Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PeciSxReset;
+
+/** Offset 0x00F8
+**/
+ UINT8 UnusedUpdSpace2[4];
+
+/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x00FD - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x00FE - HECI Timeouts
+ 0: Disable, 1: Enable (Default) timeout check for HECI
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
+/** Offset 0x00FF
+**/
+ UINT8 UnusedUpdSpace3;
+
+/** Offset 0x0100 - HECI1 BAR address
+ BAR address of HECI1
+**/
+ UINT32 Heci1BarAddress;
+
+/** Offset 0x0104 - HECI2 BAR address
+ BAR address of HECI2
+**/
+ UINT32 Heci2BarAddress;
+
+/** Offset 0x0108 - HECI3 BAR address
+ BAR address of HECI3
+**/
+ UINT32 Heci3BarAddress;
+
+/** Offset 0x010C - SG dGPU Power Delay
+ SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
+ 300=300 microseconds
+**/
+ UINT16 SgDelayAfterPwrEn;
+
+/** Offset 0x010E - SG dGPU Reset Delay
+ SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
+ microseconds
+**/
+ UINT16 SgDelayAfterHoldReset;
+
+/** Offset 0x0110 - MMIO size adjustment for AUTO mode
+ Positive number means increasing MMIO size, Negative value means decreasing MMIO
+ size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+ UINT16 MmioSizeAdjustment;
+
+/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+ Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiGen3ProgramStaticEq;
+
+/** Offset 0x0113 - Enable/Disable PEG 0
+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+ 0:Disable, 1:Enable, 2:AUTO
+**/
+ UINT8 Peg0Enable;
+
+/** Offset 0x0114 - Enable/Disable PEG 1
+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+ 0:Disable, 1:Enable, 2:AUTO
+**/
+ UINT8 Peg1Enable;
+
+/** Offset 0x0115 - Enable/Disable PEG 2
+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+ 0:Disable, 1:Enable, 2:AUTO
+**/
+ UINT8 Peg2Enable;
+
+/** Offset 0x0116 - Enable/Disable PEG 3
+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
+ 0:Disable, 1:Enable, 2:AUTO
+**/
+ UINT8 Peg3Enable;
+
+/** Offset 0x0117 - PEG 0 Max Link Speed
+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 Peg0MaxLinkSpeed;
+
+/** Offset 0x0118 - PEG 1 Max Link Speed
+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 Peg1MaxLinkSpeed;
+
+/** Offset 0x0119 - PEG 2 Max Link Speed
+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 Peg2MaxLinkSpeed;
+
+/** Offset 0x011A - PEG 3 Max Link Speed
+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 Peg3MaxLinkSpeed;
+
+/** Offset 0x011B - PEG 0 Max Link Width
+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+ Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
+ 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
+**/
+ UINT8 Peg0MaxLinkWidth;
+
+/** Offset 0x011C - PEG 1 Max Link Width
+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+ Limit Link to x2, (0x3):Limit Link to x4
+ 0:Auto, 1:x1, 2:x2, 3:x4
+**/
+ UINT8 Peg1MaxLinkWidth;
+
+/** Offset 0x011D - PEG 2 Max Link Width
+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+ Limit Link to x2
+ 0:Auto, 1:x1, 2:x2
+**/
+ UINT8 Peg2MaxLinkWidth;
+
+/** Offset 0x011E - PEG 3 Max Link Width
+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
+ Limit Link to x2
+ 0:Auto, 1:x1, 2:x2
+**/
+ UINT8 Peg3MaxLinkWidth;
+
+/** Offset 0x011F - Power down unused lanes on PEG 0
+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+ on the max possible link width
+ 0:No power saving, 1:Auto
+**/
+ UINT8 Peg0PowerDownUnusedLanes;
+
+/** Offset 0x0120 - Power down unused lanes on PEG 1
+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+ on the max possible link width
+ 0:No power saving, 1:Auto
+**/
+ UINT8 Peg1PowerDownUnusedLanes;
+
+/** Offset 0x0121 - Power down unused lanes on PEG 2
+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+ on the max possible link width
+ 0:No power saving, 1:Auto
+**/
+ UINT8 Peg2PowerDownUnusedLanes;
+
+/** Offset 0x0122 - Power down unused lanes on PEG 3
+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
+ on the max possible link width
+ 0:No power saving, 1:Auto
+**/
+ UINT8 Peg3PowerDownUnusedLanes;
+
+/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom
+ Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
+ Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
+ Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
+ 0:Before, 1:After
+**/
+ UINT8 InitPcieAspmAfterOprom;
+
+/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking
+ PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
+ Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
+ 0:Normal Operation, 1:Disable SSC
+**/
+ UINT8 PegDisableSpreadSpectrumClocking;
+
+/** Offset 0x0125
+**/
+ UINT8 UnusedUpdSpace4[3];
+
+/** Offset 0x0128 - DMI Gen3 Root port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 DmiGen3RootPortPreset[8];
+
+/** Offset 0x0130 - DMI Gen3 End port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+ UINT8 DmiGen3EndPointPreset[8];
+
+/** Offset 0x0138 - DMI Gen3 End port Hint values per lane
+ Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 DmiGen3EndPointHint[8];
+
+/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control
+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
+**/
+ UINT8 DmiGen3RxCtlePeaking[4];
+
+/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping
+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
+ caused by high package temperatures for processors that implement the Intel Thermal
+ Velocity Boost (TVB) feature
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 TvbRatioClipping;
+
+/** Offset 0x0145 - Thermal Velocity Boost voltage optimization
+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 TvbVoltageOptimization;
+
+/** Offset 0x0146
+**/
+ UINT8 UnusedUpdSpace5[2];
+
+/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
+ Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
+**/
+ UINT8 PegGen3RxCtlePeaking[10];
+
+/** Offset 0x0152 - Memory data pointer for saved preset search results
+ The reference code will store the Gen3 Preset Search results in the SaDataHob's
+ PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
+ skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
+**/
+ UINT32 PegDataPtr;
+
+/** Offset 0x0156 - PEG PERST# GPIO information
+ The reference code will use the information in this structure in order to reset
+ PCIe Gen3 devices during equalization, if necessary
+**/
+ UINT8 PegGpioData[28];
+
+/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port
+ 0(Default): Disable, 1: Enable
+**/
+ UINT8 PegRootPortHPE[4];
+
+/** Offset 0x0176 - DeEmphasis control for DMI
+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+ 0: -6dB, 1: -3.5dB
+**/
+ UINT8 DmiDeEmphasis;
+
+/** Offset 0x0177 - Selection of the primary display device
+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
+**/
+ UINT8 PrimaryDisplay;
+
+/** Offset 0x0178 - Selection of iGFX GTT Memory size
+ 1=2MB, 2=4MB, 3=8MB, Default is 3
+ 1:2MB, 2:4MB, 3:8MB
+**/
+ UINT16 GttSize;
+
+/** Offset 0x017A - Temporary MMIO address for GMADR
+ The reference code will use this as Temporary MMIO address space to access GMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+ (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
+ - 0x1) (Where ApertureSize = 256MB)
+**/
+ UINT32 GmAdr;
+
+/** Offset 0x017E - Temporary MMIO address for GTTMMADR
+ The reference code will use this as Temporary MMIO address space to access GTTMMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+ UINT32 GttMmAdr;
+
+/** Offset 0x0182 - Selection of PSMI Region size
+ 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
+ 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
+**/
+ UINT8 PsmiRegionSize;
+
+/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0
+ Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
+**/
+ UINT8 SaRtd3Pcie0Gpio[24];
+
+/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1
+ Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
+**/
+ UINT8 SaRtd3Pcie1Gpio[24];
+
+/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2
+ Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
+**/
+ UINT8 SaRtd3Pcie2Gpio[24];
+
+/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3
+ Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
+**/
+ UINT8 SaRtd3Pcie3Gpio[24];
+
+/** Offset 0x01E3 - Enable/Disable MRC TXT dependency
+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+ $EN_DIS
+**/
+ UINT8 TxtImplemented;
+
+/** Offset 0x01E4 - Enable/Disable SA OcSupport
+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+ $EN_DIS
+**/
+ UINT8 SaOcSupport;
+
+/** Offset 0x01E5 - GT slice Voltage Mode
+ 0(Default): Adaptive, 1: Override
+ 0: Adaptive, 1: Override
+**/
+ UINT8 GtVoltageMode;
+
+/** Offset 0x01E6 - Maximum GTs turbo ratio override
+ 0(Default)=Minimal/Auto, 60=Maximum
+**/
+ UINT8 GtMaxOcRatio;
+
+/** Offset 0x01E7 - The voltage offset applied to GT slice
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 GtVoltageOffset;
+
+/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtVoltageOverride;
+
+/** Offset 0x01EB - adaptive voltage applied during turbo frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtExtraTurboVoltage;
+
+/** Offset 0x01ED - voltage offset applied to the SA
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 SaVoltageOffset;
+
+/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU
+ Root port Index number to indicate which PCIe root port has dGPU
+**/
+ UINT8 RootPortIndex;
+
+/** Offset 0x01F0 - Realtime Memory Timing
+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+ realtime memory timing changes after MRC_DONE.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 RealtimeMemoryTiming;
+
+/** Offset 0x01F1 - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
+**/
+ UINT8 SaIpuEnable;
+
+/** Offset 0x01F2 - IPU IMR Configuration
+ 0:IPU Camera, 1:IPU Gen Default is 0
+ 0:IPU Camera, 1:IPU Gen
+**/
+ UINT8 SaIpuImrConfiguration;
+
+/** Offset 0x01F3 - Selection of PSMI Support On/Off
+ 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
+ $EN_DIS
+**/
+ UINT8 GtPsmiSupport;
+
+/** Offset 0x01F4 - GT unslice Voltage Mode
+ 0(Default): Adaptive, 1: Override
+ 0: Adaptive, 1: Override
+**/
+ UINT8 GtusVoltageMode;
+
+/** Offset 0x01F5 - voltage offset applied to GT unslice
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtusVoltageOffset;
+
+/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtusVoltageOverride;
+
+/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtusExtraTurboVoltage;
+
+/** Offset 0x01FB - Maximum GTus turbo ratio override
+ 0(Default)=Minimal, 60=Maximum
+**/
+ UINT8 GtusMaxOcRatio;
+
+/** Offset 0x01FC - SaPreMemProductionRsvd
+ Reserved for SA Pre-Mem Production
+ $EN_DIS
+**/
+ UINT8 SaPreMemProductionRsvd[4];
+
+/** Offset 0x0200 - BIST on Reset
+ Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 BistOnReset;
+
+/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable
+ Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 SkipStopPbet;
+
+/** Offset 0x0202 - C6DRAM power gating feature
+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+ $EN_DIS
+**/
+ UINT8 EnableC6Dram;
+
+/** Offset 0x0203 - Over clocking support
+ Over clocking support; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcSupport;
+
+/** Offset 0x0204 - Over clocking Lock
+ Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 OcLock;
+
+/** Offset 0x0205 - Maximum Core Turbo Ratio Override
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
+**/
+ UINT8 CoreMaxOcRatio;
+
+/** Offset 0x0206 - Core voltage mode
+ Core voltage mode; <b>0: Adaptive</b>; 1: Override.
+ $EN_DIS
+**/
+ UINT8 CoreVoltageMode;
+
+/** Offset 0x0207
+**/
+ UINT8 UnusedUpdSpace6;
+
+/** Offset 0x0208 - Maximum clr turbo ratio override
+ Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
+**/
+ UINT8 RingMaxOcRatio;
+
+/** Offset 0x0209 - Hyper Threading Enable/Disable
+ Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 HyperThreading;
+
+/** Offset 0x020A - CPU ratio value
+ CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x020B - Boot frequency
+ Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
+ <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
+ is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
+ 0:0, 1:1, 2:2
+**/
+ UINT8 BootFrequency;
+
+/** Offset 0x020C - Number of active cores
+ Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
+ 2 </b>;<b>3: 3 </b>
+ 0:All, 1:1, 2:2, 3:3
+**/
+ UINT8 ActiveCoreCount;
+
+/** Offset 0x020D - Processor Early Power On Configuration FCLK setting
+ <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
+ 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x020E - Set JTAG power in C10 and deeper power states
+ False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
+ and deeper power states for debug purpose. <b>0: False</b>; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 JtagC10PowerGateDisable;
+
+/** Offset 0x020F - Enable or Disable VMX
+ Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x0210 - AVX2 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx2RatioOffset;
+
+/** Offset 0x0211 - AVX3 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx3RatioOffset;
+
+/** Offset 0x0212 - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+ Disable;<b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
+/** Offset 0x0213 - Core PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 CorePllVoltageOffset;
+
+/** Offset 0x0214 - core voltage override
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageOverride;
+
+/** Offset 0x0216 - Core Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageAdaptive;
+
+/** Offset 0x0218 - Core Turbo voltage Offset
+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+ UINT16 CoreVoltageOffset;
+
+/** Offset 0x021A - Ring Downbin
+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+ lower than the core ratio.0: Disable; <b>1: Enable.</b>
+ $EN_DIS
+**/
+ UINT8 RingDownBin;
+
+/** Offset 0x021B - Ring voltage mode
+ Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
+ $EN_DIS
+**/
+ UINT8 RingVoltageMode;
+
+/** Offset 0x021C - Ring voltage override
+ The ring voltage override which is applied to the entire range of cpu ring frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageOverride;
+
+/** Offset 0x021E - Ring Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageAdaptive;
+
+/** Offset 0x0220 - Ring Turbo voltage Offset
+ The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
+**/
+ UINT16 RingVoltageOffset;
+
+/** Offset 0x0222 - TjMax Offset
+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+ UINT8 TjMaxOffset;
+
+/** Offset 0x0223 - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x0224
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x0225 - EnableSgx
+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
+ 0: Disable, 1: Enable, 2: Software Control
+**/
+ UINT8 EnableSgx;
+
+/** Offset 0x0226 - Txt
+ Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 Txt;
+
+/** Offset 0x0227
+**/
+ UINT8 UnusedUpdSpace7;
+
+/** Offset 0x0228 - PrmrrSize
+ 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x022C - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x0230 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x0234 - TxtDprMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x0238 - TxtDprMemoryBase
+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+ UINT64 TxtDprMemoryBase;
+
+/** Offset 0x0240 - BiosAcmBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 BiosAcmBase;
+
+/** Offset 0x0244 - BiosAcmSize
+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+ UINT32 BiosAcmSize;
+
+/** Offset 0x0248 - ApStartupBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 ApStartupBase;
+
+/** Offset 0x024C - TgaSize
+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+ UINT32 TgaSize;
+
+/** Offset 0x0250 - TxtLcpPdBase
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+ UINT64 TxtLcpPdBase;
+
+/** Offset 0x0258 - TxtLcpPdSize
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+ UINT64 TxtLcpPdSize;
+
+/** Offset 0x0260 - IsTPMPresence
+ IsTPMPresence default values
+**/
+ UINT8 IsTPMPresence;
+
+/** Offset 0x0261 - ReservedSecurityPreMem
+ Reserved for Security Pre-Mem
+ $EN_DIS
+**/
+ UINT8 ReservedSecurityPreMem[15];
+
+/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle
+ Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtleEnable[24];
+
+/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value
+ PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtle[24];
+
+/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
+
+/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
+
+/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
+
+/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
+
+/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
+
+/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
+
+/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
+
+/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+ PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmph[24];
+
+/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
+
+/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
+
+/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
+
+/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
+
+/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
+
+/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen1EqBoostMag[8];
+
+/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
+
+/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen2EqBoostMag[8];
+
+/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
+
+/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
+**/
+ UINT8 PchSataHsioRxGen3EqBoostMag[8];
+
+/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
+
+/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen1DownscaleAmp[8];
+
+/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
+
+/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen2DownscaleAmp[8];
+
+/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
+
+/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+ PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchSataHsioTxGen3DownscaleAmp[8];
+
+/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen1DeEmphEnable[8];
+
+/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen1DeEmph[8];
+
+/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen2DeEmphEnable[8];
+
+/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen2DeEmph[8];
+
+/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchSataHsioTxGen3DeEmphEnable[8];
+
+/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchSataHsioTxGen3DeEmph[8];
+
+/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding
+ Original LPC only decodes one byte of port 80h.
+ $EN_DIS
+**/
+ UINT8 PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x0451 - PCH Port80 Route
+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+ $EN_DIS
+**/
+ UINT8 PchPort80Route;
+
+/** Offset 0x0452 - Enable SMBus ARP support
+ Enable SMBus ARP support.
+ $EN_DIS
+**/
+ UINT8 SmbusArpEnable;
+
+/** Offset 0x0453 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0454 - SMBUS Base Address
+ SMBUS Base Address (IO space).
+**/
+ UINT16 PchSmbusIoBase;
+
+/** Offset 0x0456 - Size of PCIe IMR.
+ Size of PCIe IMR in megabytes
+**/
+ UINT16 PcieImrSize;
+
+/** Offset 0x0458 - Point of RsvdSmbusAddressTable
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+**/
+ UINT32 RsvdSmbusAddressTablePtr;
+
+/** Offset 0x045C - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x0460 - Enable PCIe IMR
+ 0:Disable, 1:Enable
+ $EN_DIS
+**/
+ UINT8 PcieImrEnabled;
+
+/** Offset 0x0461 - Root port number for IMR.
+ Root port number for IMR.
+**/
+ UINT8 ImrRpSelection;
+
+/** Offset 0x0462 - Enable SMBus Alert Pin
+ Enable SMBus Alert Pin.
+ $EN_DIS
+**/
+ UINT8 PchSmbAlertEnable;
+
+/** Offset 0x0463 - ReservedPchPreMem
+ Reserved for Pch Pre-Mem
+ $EN_DIS
+**/
+ UINT8 ReservedPchPreMem[13];
+
+/** Offset 0x0470 - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x0471 - PcdSerialIoUartNumber
+ Select SerialIo Uart Controller for debug.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIoUartNumber;
+
+/** Offset 0x0472 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x0473 - GT PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 GtPllVoltageOffset;
+
+/** Offset 0x0474 - Ring PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 RingPllVoltageOffset;
+
+/** Offset 0x0475 - System Agent PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 SaPllVoltageOffset;
+
+/** Offset 0x0476 - Memory Controller PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 McPllVoltageOffset;
+
+/** Offset 0x0477 - MRC Safe Config
+ Enables/Disable MRC Safe Config
+ $EN_DIS
+**/
+ UINT8 MrcSafeConfig;
+
+/** Offset 0x0478 - PcdSerialDebugBaudRate
+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+ 3:9600, 4:19200, 6:56700, 7:115200
+**/
+ UINT8 PcdSerialDebugBaudRate;
+
+/** Offset 0x0479 - HobBufferSize
+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+ total HOB size).
+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+ UINT8 HobBufferSize;
+
+/** Offset 0x047A - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x047B - SenseAmp Offset Training
+ Enables/Disable SenseAmp Offset Training
+ $EN_DIS
+**/
+ UINT8 SOT;
+
+/** Offset 0x047C - Early ReadMPR Timing Centering 2D
+ Enables/Disable Early ReadMPR Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDMPRTC2D;
+
+/** Offset 0x047D - Read MPR Training
+ Enables/Disable Read MPR Training
+ $EN_DIS
+**/
+ UINT8 RDMPRT;
+
+/** Offset 0x047E - Receive Enable Training
+ Enables/Disable Receive Enable Training
+ $EN_DIS
+**/
+ UINT8 RCVET;
+
+/** Offset 0x047F - Jedec Write Leveling
+ Enables/Disable Jedec Write Leveling
+ $EN_DIS
+**/
+ UINT8 JWRL;
+
+/** Offset 0x0480 - Early Write Time Centering 2D
+ Enables/Disable Early Write Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 EWRTC2D;
+
+/** Offset 0x0481 - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDTC2D;
+
+/** Offset 0x0482 - Write Timing Centering 1D
+ Enables/Disable Write Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRTC1D;
+
+/** Offset 0x0483 - Write Voltage Centering 1D
+ Enables/Disable Write Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRVC1D;
+
+/** Offset 0x0484 - Read Timing Centering 1D
+ Enables/Disable Read Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDTC1D;
+
+/** Offset 0x0485 - Dimm ODT Training
+ Enables/Disable Dimm ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTT;
+
+/** Offset 0x0486 - DIMM RON Training
+ Enables/Disable DIMM RON Training
+ $EN_DIS
+**/
+ UINT8 DIMMRONT;
+
+/** Offset 0x0487 - Write Drive Strength/Equalization 2D
+ Enables/Disable Write Drive Strength/Equalization 2D
+ $EN_DIS
+**/
+ UINT8 WRDSEQT;
+
+/** Offset 0x0488 - Write Slew Rate Training
+ Enables/Disable Write Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 WRSRT;
+
+/** Offset 0x0489 - Read ODT Training
+ Enables/Disable Read ODT Training
+ $EN_DIS
+**/
+ UINT8 RDODTT;
+
+/** Offset 0x048A - Read Equalization Training
+ Enables/Disable Read Equalization Training
+ $EN_DIS
+**/
+ UINT8 RDEQT;
+
+/** Offset 0x048B - Read Amplifier Training
+ Enables/Disable Read Amplifier Training
+ $EN_DIS
+**/
+ UINT8 RDAPT;
+
+/** Offset 0x048C - Write Timing Centering 2D
+ Enables/Disable Write Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRTC2D;
+
+/** Offset 0x048D - Read Timing Centering 2D
+ Enables/Disable Read Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDTC2D;
+
+/** Offset 0x048E - Write Voltage Centering 2D
+ Enables/Disable Write Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRVC2D;
+
+/** Offset 0x048F - Read Voltage Centering 2D
+ Enables/Disable Read Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDVC2D;
+
+/** Offset 0x0490 - Command Voltage Centering
+ Enables/Disable Command Voltage Centering
+ $EN_DIS
+**/
+ UINT8 CMDVC;
+
+/** Offset 0x0491 - Late Command Training
+ Enables/Disable Late Command Training
+ $EN_DIS
+**/
+ UINT8 LCT;
+
+/** Offset 0x0492 - Round Trip Latency Training
+ Enables/Disable Round Trip Latency Training
+ $EN_DIS
+**/
+ UINT8 RTL;
+
+/** Offset 0x0493 - Turn Around Timing Training
+ Enables/Disable Turn Around Timing Training
+ $EN_DIS
+**/
+ UINT8 TAT;
+
+/** Offset 0x0494 - Memory Test
+ Enables/Disable Memory Test
+ $EN_DIS
+**/
+ UINT8 MEMTST;
+
+/** Offset 0x0495 - DIMM SPD Alias Test
+ Enables/Disable DIMM SPD Alias Test
+ $EN_DIS
+**/
+ UINT8 ALIASCHK;
+
+/** Offset 0x0496 - Receive Enable Centering 1D
+ Enables/Disable Receive Enable Centering 1D
+ $EN_DIS
+**/
+ UINT8 RCVENC1D;
+
+/** Offset 0x0497 - Retrain Margin Check
+ Enables/Disable Retrain Margin Check
+ $EN_DIS
+**/
+ UINT8 RMC;
+
+/** Offset 0x0498 - Write Drive Strength Up/Dn independently
+ Enables/Disable Write Drive Strength Up/Dn independently
+ $EN_DIS
+**/
+ UINT8 WRDSUDT;
+
+/** Offset 0x0499 - ECC Support
+ Enables/Disable ECC Support
+ $EN_DIS
+**/
+ UINT8 EccSupport;
+
+/** Offset 0x049A - Memory Remap
+ Enables/Disable Memory Remap
+ $EN_DIS
+**/
+ UINT8 RemapEnable;
+
+/** Offset 0x049B - Rank Interleave support
+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+ the same time.
+ $EN_DIS
+**/
+ UINT8 RankInterleave;
+
+/** Offset 0x049C - Enhanced Interleave support
+ Enables/Disable Enhanced Interleave support
+ $EN_DIS
+**/
+ UINT8 EnhancedInterleave;
+
+/** Offset 0x049D - Memory Trace
+ Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
+ equal size. This option may change TOLUD and REMAP values as needed.
+ $EN_DIS
+**/
+ UINT8 MemoryTrace;
+
+/** Offset 0x049E - Ch Hash Support
+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT8 ChHashEnable;
+
+/** Offset 0x049F - Extern Therm Status
+ Enables/Disable Extern Therm Status
+ $EN_DIS
+**/
+ UINT8 EnableExtts;
+
+/** Offset 0x04A0 - Closed Loop Therm Manage
+ Enables/Disable Closed Loop Therm Manage
+ $EN_DIS
+**/
+ UINT8 EnableCltm;
+
+/** Offset 0x04A1 - Open Loop Therm Manage
+ Enables/Disable Open Loop Therm Manage
+ $EN_DIS
+**/
+ UINT8 EnableOltm;
+
+/** Offset 0x04A2 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter
+ $EN_DIS
+**/
+ UINT8 EnablePwrDn;
+
+/** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDnLpddr;
+
+/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values
+ Enables/Disable Use user provided power weights, scale factor, and channel power
+ floor values
+ $EN_DIS
+**/
+ UINT8 UserPowerWeightsEn;
+
+/** Offset 0x04A5 - RAPL PL Lock
+ Enables/Disable RAPL PL Lock
+ $EN_DIS
+**/
+ UINT8 RaplLim2Lock;
+
+/** Offset 0x04A6 - RAPL PL 2 enable
+ Enables/Disable RAPL PL 2 enable
+ $EN_DIS
+**/
+ UINT8 RaplLim2Ena;
+
+/** Offset 0x04A7 - RAPL PL 1 enable
+ Enables/Disable RAPL PL 1 enable
+ $EN_DIS
+**/
+ UINT8 RaplLim1Ena;
+
+/** Offset 0x04A8 - SelfRefresh Enable
+ Enables/Disable SelfRefresh Enable
+ $EN_DIS
+**/
+ UINT8 SrefCfgEna;
+
+/** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR
+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x04AA - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeat;
+
+/** Offset 0x04AB - Enable RH Prevention
+ Enables/Disable RH Prevention
+ $EN_DIS
+**/
+ UINT8 RhPrevention;
+
+/** Offset 0x04AC - Exit On Failure (MRC)
+ Enables/Disable Exit On Failure (MRC)
+ $EN_DIS
+**/
+ UINT8 ExitOnFailure;
+
+/** Offset 0x04AD - LPDDR Thermal Sensor
+ Enables/Disable LPDDR Thermal Sensor
+ $EN_DIS
+**/
+ UINT8 DdrThermalSensor;
+
+/** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedClock;
+
+/** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedZq;
+
+/** Offset 0x04B0 - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x04B2 - Base reference clock value
+ Base reference clock value, in Hertz(Default is 125Hz)
+ 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
+**/
+ UINT32 BClkFrequency;
+
+/** Offset 0x04B6 - Ch Hash Interleaved Bit
+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+ UINT8 ChHashInterleaveBit;
+
+/** Offset 0x04B7 - Energy Scale Factor
+ Energy Scale Factor, Default is 4
+**/
+ UINT8 EnergyScaleFact;
+
+/** Offset 0x04B8 - EPG DIMM Idd3N
+ Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
+ a per DIMM basis. Default is 26
+**/
+ UINT16 Idd3n;
+
+/** Offset 0x04BA - EPG DIMM Idd3P
+ Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
+ on a per DIMM basis. Default is 11
+**/
+ UINT16 Idd3p;
+
+/** Offset 0x04BC - CMD Slew Rate Training
+ Enable/Disable CMD Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 CMDSR;
+
+/** Offset 0x04BD - CMD Drive Strength and Tx Equalization
+ Enable/Disable CMD Drive Strength and Tx Equalization
+ $EN_DIS
+**/
+ UINT8 CMDDSEQ;
+
+/** Offset 0x04BE - CMD Normalization
+ Enable/Disable CMD Normalization
+ $EN_DIS
+**/
+ UINT8 CMDNORM;
+
+/** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training
+ Enable/Disable Early DQ Write Drive Strength and Equalization Training
+ $EN_DIS
+**/
+ UINT8 EWRDSEQ;
+
+/** Offset 0x04C0 - RH Activation Probability
+ RH Activation Probability, Probability value is 1/2^(inputvalue)
+**/
+ UINT8 RhActProbability;
+
+/** Offset 0x04C1 - RAPL PL 2 WindowX
+ Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+ UINT8 RaplLim2WindX;
+
+/** Offset 0x04C2 - RAPL PL 2 WindowY
+ Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+ UINT8 RaplLim2WindY;
+
+/** Offset 0x04C3 - RAPL PL 1 WindowX
+ Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+ UINT8 RaplLim1WindX;
+
+/** Offset 0x04C4 - RAPL PL 1 WindowY
+ Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
+**/
+ UINT8 RaplLim1WindY;
+
+/** Offset 0x04C5 - RAPL PL 2 Power
+ range[0;2^14-1]= [2047.875;0]in W, (224= Def)
+**/
+ UINT16 RaplLim2Pwr;
+
+/** Offset 0x04C7 - RAPL PL 1 Power
+ range[0;2^14-1]= [2047.875;0]in W, (224= Def)
+**/
+ UINT16 RaplLim1Pwr;
+
+/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 WarmThresholdCh0Dimm0;
+
+/** Offset 0x04CA - Warm Threshold Ch0 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 WarmThresholdCh0Dimm1;
+
+/** Offset 0x04CB - Warm Threshold Ch1 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 WarmThresholdCh1Dimm0;
+
+/** Offset 0x04CC - Warm Threshold Ch1 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 WarmThresholdCh1Dimm1;
+
+/** Offset 0x04CD - Hot Threshold Ch0 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 HotThresholdCh0Dimm0;
+
+/** Offset 0x04CE - Hot Threshold Ch0 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 HotThresholdCh0Dimm1;
+
+/** Offset 0x04CF - Hot Threshold Ch1 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 HotThresholdCh1Dimm0;
+
+/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
+**/
+ UINT8 HotThresholdCh1Dimm1;
+
+/** Offset 0x04D1 - Warm Budget Ch0 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 WarmBudgetCh0Dimm0;
+
+/** Offset 0x04D2 - Warm Budget Ch0 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 WarmBudgetCh0Dimm1;
+
+/** Offset 0x04D3 - Warm Budget Ch1 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 WarmBudgetCh1Dimm0;
+
+/** Offset 0x04D4 - Warm Budget Ch1 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 WarmBudgetCh1Dimm1;
+
+/** Offset 0x04D5 - Hot Budget Ch0 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 HotBudgetCh0Dimm0;
+
+/** Offset 0x04D6 - Hot Budget Ch0 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 HotBudgetCh0Dimm1;
+
+/** Offset 0x04D7 - Hot Budget Ch1 Dimm0
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 HotBudgetCh1Dimm0;
+
+/** Offset 0x04D8 - Hot Budget Ch1 Dimm1
+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
+**/
+ UINT8 HotBudgetCh1Dimm1;
+
+/** Offset 0x04D9 - Idle Energy Ch0Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyCh0Dimm0;
+
+/** Offset 0x04DA - Idle Energy Ch0Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyCh0Dimm1;
+
+/** Offset 0x04DB - Idle Energy Ch1Dimm0
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyCh1Dimm0;
+
+/** Offset 0x04DC - Idle Energy Ch1Dimm1
+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
+**/
+ UINT8 IdleEnergyCh1Dimm1;
+
+/** Offset 0x04DD - PowerDown Energy Ch0Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+ UINT8 PdEnergyCh0Dimm0;
+
+/** Offset 0x04DE - PowerDown Energy Ch0Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+ UINT8 PdEnergyCh0Dimm1;
+
+/** Offset 0x04DF - PowerDown Energy Ch1Dimm0
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+ UINT8 PdEnergyCh1Dimm0;
+
+/** Offset 0x04E0 - PowerDown Energy Ch1Dimm1
+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
+**/
+ UINT8 PdEnergyCh1Dimm1;
+
+/** Offset 0x04E1 - Activate Energy Ch0Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyCh0Dimm0;
+
+/** Offset 0x04E2 - Activate Energy Ch0Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyCh0Dimm1;
+
+/** Offset 0x04E3 - Activate Energy Ch1Dimm0
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyCh1Dimm0;
+
+/** Offset 0x04E4 - Activate Energy Ch1Dimm1
+ Activate Energy Contribution, range[255;0],(172= Def)
+**/
+ UINT8 ActEnergyCh1Dimm1;
+
+/** Offset 0x04E5 - Read Energy Ch0Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyCh0Dimm0;
+
+/** Offset 0x04E6 - Read Energy Ch0Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyCh0Dimm1;
+
+/** Offset 0x04E7 - Read Energy Ch1Dimm0
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyCh1Dimm0;
+
+/** Offset 0x04E8 - Read Energy Ch1Dimm1
+ Read Energy Contribution, range[255;0],(212= Def)
+**/
+ UINT8 RdEnergyCh1Dimm1;
+
+/** Offset 0x04E9 - Write Energy Ch0Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyCh0Dimm0;
+
+/** Offset 0x04EA - Write Energy Ch0Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyCh0Dimm1;
+
+/** Offset 0x04EB - Write Energy Ch1Dimm0
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyCh1Dimm0;
+
+/** Offset 0x04EC - Write Energy Ch1Dimm1
+ Write Energy Contribution, range[255;0],(221= Def)
+**/
+ UINT8 WrEnergyCh1Dimm1;
+
+/** Offset 0x04ED - Throttler CKEMin Timer
+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+ Dfault is 0x30
+**/
+ UINT8 ThrtCkeMinTmr;
+
+/** Offset 0x04EE - Cke Rank Mapping
+ Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
+ which rank CKE[i] goes to.
+**/
+ UINT8 CkeRankMapping;
+
+/** Offset 0x04EF - Rapl Power Floor Ch0
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh0;
+
+/** Offset 0x04F0 - Rapl Power Floor Ch1
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh1;
+
+/** Offset 0x04F1 - Command Rate Support
+ CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
+ 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
+**/
+ UINT8 EnCmdRate;
+
+/** Offset 0x04F2 - REFRESH_2X_MODE
+ 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
+ 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
+**/
+ UINT8 Refresh2X;
+
+/** Offset 0x04F3 - Energy Performance Gain
+ Enable/disable(default) Energy Performance Gain.
+ $EN_DIS
+**/
+ UINT8 EpgEnable;
+
+/** Offset 0x04F4 - Row Hammer Solution
+ Type of method used to prevent Row Hammer. Default is Hardware RHP
+ 0:Hardware RHP, 1:2x Refresh
+**/
+ UINT8 RhSolution;
+
+/** Offset 0x04F5 - User Manual Threshold
+ Disabled: Predefined threshold will be used.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserThresholdEnable;
+
+/** Offset 0x04F6 - User Manual Budget
+ Disabled: Configuration of memories will defined the Budget value.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserBudgetEnable;
+
+/** Offset 0x04F7 - TcritMax
+ Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
+ has to be greater than THIGHMax .\n
+ Critical temperature will be TcritMax
+**/
+ UINT8 TsodTcritMax;
+
+/** Offset 0x04F8 - Event mode
+ Disable:Comparator mode.\n
+ Enable:Interrupt mode
+ $EN_DIS
+**/
+ UINT8 TsodEventMode;
+
+/** Offset 0x04F9 - EVENT polarity
+ Disable:Active LOW.\n
+ Enable:Active HIGH
+ $EN_DIS
+**/
+ UINT8 TsodEventPolarity;
+
+/** Offset 0x04FA - Critical event only
+ Disable:Trips on alarm or critical.\n
+ Enable:Trips only if criticaal temperature is reached
+ $EN_DIS
+**/
+ UINT8 TsodCriticalEventOnly;
+
+/** Offset 0x04FB - Event output control
+ Disable:Event output disable.\n
+ Enable:Event output enabled
+ $EN_DIS
+**/
+ UINT8 TsodEventOutputControl;
+
+/** Offset 0x04FC - Alarm window lock bit
+ Disable:Alarm trips are not locked and can be changed.\n
+ Enable:Alarm trips are locked and cannot be changed
+ $EN_DIS
+**/
+ UINT8 TsodAlarmwindowLockBit;
+
+/** Offset 0x04FD - Critical trip lock bit
+ Disable:Critical trip is not locked and can be changed.\n
+ Enable:Critical trip is locked and cannot be changed
+ $EN_DIS
+**/
+ UINT8 TsodCriticaltripLockBit;
+
+/** Offset 0x04FE - Shutdown mode
+ Disable:Temperature sensor enable.\n
+ Enable:Temperature sensor disable
+ $EN_DIS
+**/
+ UINT8 TsodShutdownMode;
+
+/** Offset 0x04FF - ThighMax
+ Thigh = ThighMax (Default is 93)
+**/
+ UINT8 TsodThigMax;
+
+/** Offset 0x0500 - User Manual Thig and Tcrit
+ Disabled(Default): Temperature will be given by the configuration of memories and
+ 1x or 2xrefresh rate.\n
+ Enabled: User Input will define for Thigh and Tcrit.
+ $EN_DIS
+**/
+ UINT8 TsodManualEnable;
+
+/** Offset 0x0501 - Force OLTM or 2X Refresh when needed
+ Disabled(Default): = Force OLTM.\n
+ Enabled: = Force 2x Refresh.
+ $EN_DIS
+**/
+ UINT8 ForceOltmOrRefresh2x;
+
+/** Offset 0x0502 - Pwr Down Idle Timer
+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+ AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+ UINT8 PwdwnIdleCounter;
+
+/** Offset 0x0503 - Bitmask of ranks that have CA bus terminated
+ Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
+ Rank0 is terminating and Rank1 is non-terminating</b>
+**/
+ UINT8 CmdRanksTerminated;
+
+/** Offset 0x0504 - GDXC MOT enable
+ GDXC MOT enable.
+ $EN_DIS
+**/
+ UINT8 GdxcEnable;
+
+/** Offset 0x0505 - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x0506 - Fivr Faults
+ Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
+ $EN_DIS
+**/
+ UINT8 FivrFaults;
+
+/** Offset 0x0507 - Fivr Efficiency
+ Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
+ $EN_DIS
+**/
+ UINT8 FivrEfficiency;
+
+/** Offset 0x0508 - Safe Mode Support
+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+ $EN_DIS
+**/
+ UINT8 SafeMode;
+
+/** Offset 0x0509 - Ask MRC to clear memory content
+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x050A - LpDdrDqDqsReTraining
+ Enables/Disable LpDdrDqDqsReTraining
+ $EN_DIS
+**/
+ UINT8 LpDdrDqDqsReTraining;
+
+/** Offset 0x050B - Post Code Output Port
+ This option configures Post Code Output Port
+**/
+ UINT16 PostCodeOutputPort;
+
+/** Offset 0x050D - RMTLoopCount
+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+ UINT8 RMTLoopCount;
+
+/** Offset 0x050E - BER Support
+ Enable/Disable the Rank Margin Tool interpolation/extrapolation.
+ 0:Disable, 1:Enable
+**/
+ UINT8 EnBER;
+
+/** Offset 0x050F - Dual Dimm Per-Channel Board Type
+ Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
+ to limit maximum frequency for some SKUs.
+ 0:1DPC, 1:2DPC
+**/
+ UINT8 DualDimmPerChannelBoardType;
+
+/** Offset 0x0510
+**/
+ UINT8 ReservedFspmUpd[15];
+} FSP_M_CONFIG;
+
+/** Fsp M Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x0520
+**/
+ UINT32 Signature;
+
+/** Offset 0x0524 - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x0525 - Generate BIOS Data ACPI Table
+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+ $EN_DIS
+**/
+ UINT8 BdatEnable;
+
+/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
+ Detect and report if external graphics device only support LegacyOpROM or not (to
+ support CSM auto-enable). Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 ScanExtGfxForLegacyOpRom;
+
+/** Offset 0x0527 - Lock PCU Thermal Management registers
+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 LockPTMregs;
+
+/** Offset 0x0528 - DMI Max Link Speed
+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 DmiMaxLinkSpeed;
+
+/** Offset 0x0529 - DMI Equalization Phase 2
+ DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
+ AUTO - Use the current default method
+ 0:Disable phase2, 1:Enable phase2, 2:Auto
+**/
+ UINT8 DmiGen3EqPh2Enable;
+
+/** Offset 0x052A - DMI Gen3 Equalization Phase3
+ DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 DmiGen3EqPh3Method;
+
+/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.
+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+ Enable phase 2, Auto(0x2)(Default): Use the current default method
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Peg0Gen3EqPh2Enable;
+
+/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.
+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+ Enable phase 2, Auto(0x2)(Default): Use the current default method
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Peg1Gen3EqPh2Enable;
+
+/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.
+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+ Enable phase 2, Auto(0x2)(Default): Use the current default method
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Peg2Gen3EqPh2Enable;
+
+/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.
+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
+ Enable phase 2, Auto(0x2)(Default): Use the current default method
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Peg3Gen3EqPh2Enable;
+
+/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.
+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 Peg0Gen3EqPh3Method;
+
+/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.
+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 Peg1Gen3EqPh3Method;
+
+/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.
+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 Peg2Gen3EqPh3Method;
+
+/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.
+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 Peg3Gen3EqPh3Method;
+
+/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
+ Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 PegGen3ProgramStaticEq;
+
+/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
+ Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
+ Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
+ and generate new EQ values every boot, not recommended
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen3SwEqAlwaysAttempt;
+
+/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
+ Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
+ Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
+ current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
+ for this default to change over time;using Auto will ensure Reference Code always
+ uses the latest default settings
+ 0:P7 P3 P5, 1:P0 to P9, 2:Auto
+**/
+ UINT8 Gen3SwEqNumberOfPresets;
+
+/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
+ Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
+ Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
+ Use the current default
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 Gen3SwEqEnableVocTest;
+
+/** Offset 0x0537 - PCIe Rx Compliance Testing Mode
+ Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
+ PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
+ it should only be set when doing PCIe compliance testing
+ $EN_DIS
+**/
+ UINT8 PegRxCemTestingMode;
+
+/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
+ the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
+**/
+ UINT8 PegRxCemLoopbackLane;
+
+/** Offset 0x0539 - Generate PCIe BDAT Margin Table
+ Set this policy to enable the generation and addition of PCIe margin data to the
+ BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
+ data generation, Enable(0x1): Generate PCIe BDAT margin data
+ $EN_DIS
+**/
+ UINT8 PegGenerateBdatMarginTable;
+
+/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing
+ Set this policy to enable the generation and addition of PCIe margin data to the
+ BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
+ Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
+ compliance testing
+ $EN_DIS
+**/
+ UINT8 PegRxCemNonProtocolAwareness;
+
+/** Offset 0x053B - PCIe Override RxCTLE
+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+ peak values unmodified
+ $EN_DIS
+**/
+ UINT8 PegGen3RxCtleOverride;
+
+/** Offset 0x053C - Rsvd
+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
+ peak values unmodified
+ $EN_DIS
+**/
+ UINT8 PegGen3Rsvd;
+
+/** Offset 0x053D - PEG Gen3 Root port preset values per lane
+ Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 PegGen3RootPortPreset[20];
+
+/** Offset 0x0551 - PEG Gen3 End port preset values per lane
+ Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+ UINT8 PegGen3EndPointPreset[20];
+
+/** Offset 0x0565 - PEG Gen3 End port Hint values per lane
+ Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 PegGen3EndPointHint[20];
+
+/** Offset 0x0579
+**/
+ UINT8 UnusedUpdSpace9;
+
+/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
+ Range: 0-65535, default is 1000. @warning Do not change from the default
+**/
+ UINT16 Gen3SwEqJitterDwellTime;
+
+/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization
+ Range: 0-65535, default is 1. @warning Do not change from the default
+**/
+ UINT16 Gen3SwEqJitterErrorTarget;
+
+/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization
+ Range: 0-65535, default is 10000. @warning Do not change from the default
+**/
+ UINT16 Gen3SwEqVocDwellTime;
+
+/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization
+ Range: 0-65535, default is 2. @warning Do not change from the default
+**/
+ UINT16 Gen3SwEqVocErrorTarget;
+
+/** Offset 0x0582 - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x0583 - BdatTestType
+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+ 0:Rank Margin Tool, 1:Margin2D
+**/
+ UINT8 BdatTestType;
+
+/** Offset 0x0584 - SaPreMemTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPreMemTestRsvd[12];
+
+/** Offset 0x0590 - TotalFlashSize
+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+ UINT16 TotalFlashSize;
+
+/** Offset 0x0592 - BiosSize
+ Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x0594 - TxtAcheckRequest
+ Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
+ $EN_DIS
+**/
+ UINT8 TxtAcheckRequest;
+
+/** Offset 0x0595 - SecurityTestRsvd
+ Reserved for SA Pre-Mem Test
+ $EN_DIS
+**/
+ UINT8 SecurityTestRsvd[3];
+
+/** Offset 0x0598 - Smbus dynamic power gating
+ Disable or Enable Smbus dynamic power gating.
+ $EN_DIS
+**/
+ UINT8 SmbusDynamicPowerGating;
+
+/** Offset 0x0599 - Disable and Lock Watch Dog Register
+ Set 1 to clear WDT status, then disable and lock WDT registers.
+ $EN_DIS
+**/
+ UINT8 WdtDisableAndLock;
+
+/** Offset 0x059A - SMBUS SPD Write Disable
+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+ Disable bit. For security recommendations, SPD write disable bit must be set.
+ $EN_DIS
+**/
+ UINT8 SmbusSpdWriteDisable;
+
+/** Offset 0x059B - ChipsetInit HECI message
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
+ If disabled, it prevents from sending ChipsetInit HECI message.
+ $EN_DIS
+**/
+ UINT8 ChipsetInitMessage;
+
+/** Offset 0x059C - Bypass ChipsetInit sync reset.
+ 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
+ $EN_DIS
+**/
+ UINT8 BypassPhySyncReset;
+
+/** Offset 0x059D - Force ME DID Init Status
+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+ ME DID init stat value
+ $EN_DIS
+**/
+ UINT8 DidInitStat;
+
+/** Offset 0x059E - CPU Replaced Polling Disable
+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+ $EN_DIS
+**/
+ UINT8 DisableCpuReplacedPolling;
+
+/** Offset 0x059F - ME DID Message
+ Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
+ the DID message from being sent)
+ $EN_DIS
+**/
+ UINT8 SendDidMsg;
+
+/** Offset 0x05A0 - Retry mechanism for HECI APIs
+ Test, 0: disable, 1: enable, Enable/Disable HECI retry.
+ $EN_DIS
+**/
+ UINT8 DisableHeciRetry;
+
+/** Offset 0x05A1 - Check HECI message before send
+ Test, 0: disable, 1: enable, Enable/Disable message check.
+ $EN_DIS
+**/
+ UINT8 DisableMessageCheck;
+
+/** Offset 0x05A2 - Skip MBP HOB
+ Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
+ $EN_DIS
+**/
+ UINT8 SkipMbpHob;
+
+/** Offset 0x05A3 - HECI2 Interface Communication
+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+ $EN_DIS
+**/
+ UINT8 HeciCommunication2;
+
+/** Offset 0x05A4 - Enable KT device
+ Test, 0: disable, 1: enable, Enable or Disable KT device.
+ $EN_DIS
+**/
+ UINT8 KtDeviceEnable;
+
+/** Offset 0x05A5 - tRd2RdSG
+ Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2RdSG;
+
+/** Offset 0x05A6 - tRd2RdDG
+ Delay between Read-to-Read commands in different Bank Group for DDR4. All other
+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2RdDG;
+
+/** Offset 0x05A7 - tRd2RdDR
+ Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2RdDR;
+
+/** Offset 0x05A8 - tRd2RdDD
+ Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2RdDD;
+
+/** Offset 0x05A9 - tWr2RdSG
+ Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.
+**/
+ UINT8 tWr2RdSG;
+
+/** Offset 0x05AA - tWr2RdDG
+ Delay between Write-to-Read commands in different Bank Group for DDR4. All other
+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2RdDG;
+
+/** Offset 0x05AB - tWr2RdDR
+ Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2RdDR;
+
+/** Offset 0x05AC - tWr2RdDD
+ Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2RdDD;
+
+/** Offset 0x05AD - tWr2WrSG
+ Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2WrSG;
+
+/** Offset 0x05AE - tWr2WrDG
+ Delay between Write-to-Write commands in different Bank Group for DDR4. All other
+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2WrDG;
+
+/** Offset 0x05AF - tWr2WrDR
+ Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2WrDR;
+
+/** Offset 0x05B0 - tWr2WrDD
+ Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+ UINT8 tWr2WrDD;
+
+/** Offset 0x05B1 - tRd2WrSG
+ Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2WrSG;
+
+/** Offset 0x05B2 - tRd2WrDG
+ Delay between Read-to-Write commands in different Bank Group for DDR4. All other
+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2WrDG;
+
+/** Offset 0x05B3 - tRd2WrDR
+ Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2WrDR;
+
+/** Offset 0x05B4 - tRd2WrDD
+ Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
+**/
+ UINT8 tRd2WrDD;
+
+/** Offset 0x05B5 - tRRD_L
+ Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31
+**/
+ UINT8 tRRD_L;
+
+/** Offset 0x05B6 - tRRD_S
+ Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:
+ AUTO, max: 31
+**/
+ UINT8 tRRD_S;
+
+/** Offset 0x05B7 - tWTR_L
+ Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:
+ AUTO, max: 60
+**/
+ UINT8 tWTR_L;
+
+/** Offset 0x05B8 - tWTR_S
+ Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.
+ 0: AUTO, max: 28
+**/
+ UINT8 tWTR_S;
+
+/** Offset 0x05B9
+**/
+ UINT8 ReservedFspmTestUpd[3];
+} FSP_M_TEST_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x051F
+**/
+ UINT8 UnusedUpdSpace8;
+
+/** Offset 0x0520
+**/
+ FSP_M_TEST_CONFIG FspmTestConfig;
+
+/** Offset 0x05BC
+**/
+ UINT32 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
new file mode 100644
index 0000000..5725dd3
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
@@ -0,0 +1,3243 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - Logo Pointer
+ Points to PEI Display Logo Image
+**/
+ UINT32 LogoPtr;
+
+/** Offset 0x0024 - Logo Size
+ Size of PEI Display Logo Image
+**/
+ UINT32 LogoSize;
+
+/** Offset 0x0028 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x002C - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x002D - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x002E
+**/
+ UINT8 UnusedUpdSpace0[3];
+
+/** Offset 0x0031 - Enable eMMC Controller
+ Enable/disable eMMC Controller.
+ $EN_DIS
+**/
+ UINT8 ScsEmmcEnabled;
+
+/** Offset 0x0032 - Enable eMMC HS400 Mode
+ Enable eMMC HS400 Mode.
+ $EN_DIS
+**/
+ UINT8 ScsEmmcHs400Enabled;
+
+/** Offset 0x0033 - Enable SdCard Controller
+ Enable/disable SD Card Controller.
+ $EN_DIS
+**/
+ UINT8 ScsSdCardEnabled;
+
+/** Offset 0x0034 - Show SPI controller
+ Enable/disable to show SPI controller.
+ $EN_DIS
+**/
+ UINT8 ShowSpiController;
+
+/** Offset 0x0035
+**/
+ UINT8 UnusedUpdSpace1[3];
+
+/** Offset 0x0038 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x003C - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0040 - Turbo Mode
+ Enable/Disable Turbo mode. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 TurboMode;
+
+/** Offset 0x0041 - Enable SATA SALP Support
+ Enable/disable SATA Aggressive Link Power Management.
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0042 - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+ and so on.
+**/
+ UINT8 SataPortsEnable[8];
+
+/** Offset 0x004A - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+ port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlp[8];
+
+/** Offset 0x0052 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x0062 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x006C - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x006D
+**/
+ UINT8 UnusedUpdSpace2[2];
+
+/** Offset 0x006F - Enable SerialIo Device Mode
+ 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable
+ SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device
+ mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,
+ and so on.
+**/
+ UINT8 SerialIoDevMode[12];
+
+/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+ UINT32 DevIntConfigPtr;
+
+/** Offset 0x007F - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
+**/
+ UINT8 NumOfDevIntConfig;
+
+/** Offset 0x0080 - PIRQx to IRQx Map Config
+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
+ 8259 PCI mode.
+**/
+ UINT8 PxRcConfig[8];
+
+/** Offset 0x0088 - Select GPIO IRQ Route
+ GPIO IRQ Select. The valid value is 14 or 15.
+**/
+ UINT8 GpioIrqRoute;
+
+/** Offset 0x0089 - Select SciIrqSelect
+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+ UINT8 SciIrqSelect;
+
+/** Offset 0x008A - Select TcoIrqSelect
+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+ UINT8 TcoIrqSelect;
+
+/** Offset 0x008B - Enable/Disable Tco IRQ
+ Enable/disable TCO IRQ
+ $EN_DIS
+**/
+ UINT8 TcoIrqEnable;
+
+/** Offset 0x008C - PCH HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ UINT8 PchHdaVerbTableEntryNum;
+
+/** Offset 0x008D - PCH HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ UINT32 PchHdaVerbTablePtr;
+
+/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability
+ Capability to detect wake initiated by a codec in Sx
+**/
+ UINT8 PchHdaCodecSxWakeCapability;
+
+/** Offset 0x0092 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ UINT8 SataEnable;
+
+/** Offset 0x0093 - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x0094 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2AfePetxiset[16];
+
+/** Offset 0x00A4 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2AfeTxiset[16];
+
+/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2AfePredeemp[16];
+
+/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2AfePehalfbit[16];
+
+/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+ = 00h</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x00FC - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x00FD - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHda;
+
+/** Offset 0x00FE - Enable HD Audio DMIC0 Link
+ Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkDmic0;
+
+/** Offset 0x00FF - Enable HD Audio DMIC1 Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkDmic1;
+
+/** Offset 0x0100 - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp0;
+
+/** Offset 0x0101 - Enable HD Audio SSP1 Link
+ Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp1;
+
+/** Offset 0x0102 - Enable HD Audio SSP2 Link
+ Enable/disable HD Audio SSP2/I2S link.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSsp2;
+
+/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link
+ Enable/disable HD Audio SNDW1 link. Muxed with HDA.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw1;
+
+/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link
+ Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw2;
+
+/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link
+ Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw3;
+
+/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link
+ Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkSndw4;
+
+/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting
+ 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
+ $EN_DIS
+**/
+ UINT8 PchHdaSndwBufferRcomp;
+
+/** Offset 0x0108 - PTM for PCIE RP Mask
+ Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpPtmMask;
+
+/** Offset 0x010C - DPC for PCIE RP Mask
+ Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
+ One bit for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpDpcMask;
+
+/** Offset 0x0110 - DPC Extensions PCIE RP Mask
+ Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
+ for each port, bit0 for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpDpcExtensionsMask;
+
+/** Offset 0x0114 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x0115 - Power button debounce configuration
+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+ UINT32 PmcPowerButtonDebounce;
+
+/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled
+ PCH eSPI Master and Slave BME enabled
+ $EN_DIS
+**/
+ UINT8 PchEspiBmeMasterSlaveEnabled;
+
+/** Offset 0x011A - PCH SATA use RST Legacy OROM
+ Use PCH SATA RST Legacy OROM when CSM is Enabled
+ $EN_DIS
+**/
+ UINT8 SataRstLegacyOrom;
+
+/** Offset 0x011B - Trace Hub Memory Base
+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
+ memory is configured properly.
+**/
+ UINT32 TraceHubMemBase;
+
+/** Offset 0x011F - PMC Debug Message Enable
+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
+ $EN_DIS
+**/
+ UINT8 PmcDbgMsgEn;
+
+/** Offset 0x0120 - PchPostMemRsvd
+ Reserved for PCH Post-Mem
+ $EN_DIS
+**/
+ UINT8 PchPostMemRsvd[37];
+
+/** Offset 0x0145 - Enable Ufs Controller
+ Enable/disable Ufs 2.0 Controller.
+ $EN_DIS
+**/
+ UINT8 ScsUfsEnabled;
+
+/** Offset 0x0146 - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 PchCnviMode;
+
+/** Offset 0x0147 - SdCard power enable polarity
+ Choose SD_PWREN# polarity
+ 0: Active low, 1: Active high
+**/
+ UINT8 SdCardPowerEnableActiveHigh;
+
+/** Offset 0x0148 - PCH USB2 PHY Power Gating enable
+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+ Sus Well PG
+ $EN_DIS
+**/
+ UINT8 PchUsb2PhySusPgEnable;
+
+/** Offset 0x0149 - PCH USB OverCurrent mapping enable
+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+ mapping allow for NOA usage of OC pins
+ $EN_DIS
+**/
+ UINT8 PchUsbOverCurrentEnable;
+
+/** Offset 0x014A
+**/
+ UINT8 UnusedUpdSpace3;
+
+/** Offset 0x014B - CNVi MfUart1 Type
+ This option configures Uart type which connects to MfUart1
+ 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads
+**/
+ UINT8 PchCnviMfUart1Type;
+
+/** Offset 0x014C - Espi Lgmr Memory Range decode
+ This option enables or disables espi lgmr
+ $EN_DIS
+**/
+ UINT8 PchEspiLgmrEnable;
+
+/** Offset 0x014D - HECI3 state
+ The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
+ 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 Heci3Enabled;
+
+/** Offset 0x014E
+**/
+ UINT8 UnusedUpdSpace4;
+
+/** Offset 0x014F - PCHHOT# pin
+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchHotEnable;
+
+/** Offset 0x0150 - SATA LED
+ SATA LED indicating SATA controller activity. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 SataLedEnable;
+
+/** Offset 0x0151 - VRAlert# Pin
+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmVrAlert;
+
+/** Offset 0x0152 - SLP_S0 VM Dynamic Control
+ SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmSlpS0VmRuntimeControl;
+
+/** Offset 0x0153 - SLP_S0 VM 0.70V Support
+ SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmSlpS0Vm070VSupport;
+
+/** Offset 0x0154 - SLP_S0 VM 0.75V Support
+ SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmSlpS0Vm075VSupport;
+
+/** Offset 0x0155 - AMT Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+ $EN_DIS
+**/
+ UINT8 AmtEnabled;
+
+/** Offset 0x0156 - WatchDog Timer Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
+ $EN_DIS
+**/
+ UINT8 WatchDog;
+
+/** Offset 0x0157 - ASF Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
+ $EN_DIS
+**/
+ UINT8 AsfEnabled;
+
+/** Offset 0x0158 - Manageability Mode set by Mebx
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
+ $EN_DIS
+**/
+ UINT8 ManageabilityMode;
+
+/** Offset 0x0159 - PET Progress
+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
+ PET Events.
+ $EN_DIS
+**/
+ UINT8 FwProgress;
+
+/** Offset 0x015A - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
+ $EN_DIS
+**/
+ UINT8 AmtSolEnabled;
+
+/** Offset 0x015B - OS Timer
+ 16 bits Value, Set OS watchdog timer.
+ $EN_DIS
+**/
+ UINT16 WatchDogTimerOs;
+
+/** Offset 0x015D - BIOS Timer
+ 16 bits Value, Set BIOS watchdog timer.
+ $EN_DIS
+**/
+ UINT16 WatchDogTimerBios;
+
+/** Offset 0x015F - Remote Assistance Trigger Availablilty
+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
+ $EN_DIS
+**/
+ UINT8 RemoteAssistance;
+
+/** Offset 0x0160 - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
+ $EN_DIS
+**/
+ UINT8 AmtKvmEnabled;
+
+/** Offset 0x0161 - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
+ $EN_DIS
+**/
+ UINT8 ForcMebxSyncUp;
+
+/** Offset 0x0162
+**/
+ UINT8 UnusedUpdSpace5[1];
+
+/** Offset 0x0163 - PCH PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 PcieRpSlotImplemented[24];
+
+/** Offset 0x017B - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+ (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[16];
+
+/** Offset 0x018B - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[16];
+
+/** Offset 0x019B - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 PcieRpAcsEnabled[24];
+
+/** Offset 0x01B3 - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 PcieRpEnableCpm[24];
+
+/** Offset 0x01CB - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+ PCH-H. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcModPhySusPgEnable;
+
+/** Offset 0x01FC - SlpS0WithGbeSupport
+ Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 SlpS0WithGbeSupport;
+
+/** Offset 0x01FD
+**/
+ UINT8 UnusedUpdSpace6[3];
+
+/** Offset 0x0200 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
+/** Offset 0x0201 - DMI ASPM
+ 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
+ 0:Disable, 1:L0s, 2:L1, 3:L0sL1
+**/
+ UINT8 DmiAspm;
+
+/** Offset 0x0202 - PCIe DeEmphasis control per root port
+ 0: -6dB, 1(Default): -3.5dB
+ 0:-6dB, 1:-3.5dB
+**/
+ UINT8 PegDeEmphasis[4];
+
+/** Offset 0x0206 - PCIe Slot Power Limit value per root port
+ Slot power limit value per root port
+**/
+ UINT8 PegSlotPowerLimitValue[4];
+
+/** Offset 0x020A - PCIe Slot Power Limit scale per root port
+ Slot power limit scale per root port
+ 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
+**/
+ UINT8 PegSlotPowerLimitScale[4];
+
+/** Offset 0x020E - PCIe Physical Slot Number per root port
+ Physical Slot Number per root port
+**/
+ UINT16 PegPhysicalSlotNumber[4];
+
+/** Offset 0x0216 - Enable/Disable PavpEnable
+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+ $EN_DIS
+**/
+ UINT8 PavpEnable;
+
+/** Offset 0x0217 - CdClock Frequency selection
+ 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz
+ 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit
+ Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x0219
+**/
+ UINT8 UnusedUpdSpace7;
+
+/** Offset 0x021A - Enable or disable GNA device
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 GnaEnable;
+
+/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 X2ApicOptOut;
+
+/** Offset 0x021C - Base addresses for VT-d function MMIO access
+ Base addresses for VT-d MMIO access per VT-d engine
+**/
+ UINT32 VtdBaseAddress[3];
+
+/** Offset 0x0228 - Enable or disable eDP device
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortEdp;
+
+/** Offset 0x0229 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x022A - Enable or disable HPD of DDI port C
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x022B - Enable or disable HPD of DDI port D
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortDHpd;
+
+/** Offset 0x022C - Enable or disable HPD of DDI port F
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortFHpd;
+
+/** Offset 0x022D - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x022E - Enable or disable DDC of DDI port C
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x022F - Enable or disable DDC of DDI port D
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortDDdc;
+
+/** Offset 0x0230 - Enable or disable DDC of DDI port F
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortFDdc;
+
+/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
+ CD clock in S3 resume due to GOP absent
+ $EN_DIS
+**/
+ UINT8 SkipS3CdClockInit;
+
+/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
+ Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
+ T12 Delay to max 500ms
+ 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
+**/
+ UINT16 DeltaT12PowerCycleDelay;
+
+/** Offset 0x0234 - Blt Buffer Address
+ Address of Blt buffer
+**/
+ UINT32 BltBufferAddress;
+
+/** Offset 0x0238 - Blt Buffer Size
+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+**/
+ UINT32 BltBufferSize;
+
+/** Offset 0x023C - SaPostMemProductionRsvd
+ Reserved for SA Post-Mem Production
+ $EN_DIS
+**/
+ UINT8 SaPostMemProductionRsvd[35];
+
+/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
+ PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
+ Alpine ridge
+**/
+ UINT8 PcieRootPortGen2PllL1CgDisable[24];
+
+/** Offset 0x0277 - Advanced Encryption Standard (AES) feature
+ Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
+ $EN_DIS
+**/
+ UINT8 AesEnable;
+
+/** Offset 0x0278 - Power State 3 enable/disable
+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
+ For all VR Indexes
+**/
+ UINT8 Psi3Enable[5];
+
+/** Offset 0x027D - Power State 4 enable/disable
+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
+ all VR Indexes
+**/
+ UINT8 Psi4Enable[5];
+
+/** Offset 0x0282 - Imon slope correction
+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
+**/
+ UINT8 ImonSlope[5];
+
+/** Offset 0x0287 - Imon offset correction
+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
+**/
+ UINT8 ImonOffset[5];
+
+/** Offset 0x028C - Enable/Disable BIOS configuration of VR
+ Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
+**/
+ UINT8 VrConfigEnable[5];
+
+/** Offset 0x0291 - Thermal Design Current enable/disable
+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
+ Enable.For all VR Indexes
+**/
+ UINT8 TdcEnable[5];
+
+/** Offset 0x0296 - HECI3 state
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
+ , 8 - 8ms , 10 - 10ms.For all VR Indexe
+**/
+ UINT8 TdcTimeWindow[5];
+
+/** Offset 0x029B - Thermal Design Current Lock
+ PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 TdcLock[5];
+
+/** Offset 0x02A0 - Platform Psys slope correction
+ PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
+ 1/100 increment values. Range is 0-200. 125 = 1.25
+**/
+ UINT8 PsysSlope;
+
+/** Offset 0x02A1 - Platform Psys offset correction
+ PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
+ Range 0-255. Value of 100 = 100/4 = 25 offset
+**/
+ UINT8 PsysOffset;
+
+/** Offset 0x02A2 - Acoustic Noise Mitigation feature
+ Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 AcousticNoiseMitigation;
+
+/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. <b>0: False</b>; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisableIa;
+
+/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain
+ Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRateForIa;
+
+/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain
+ Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRateForGt;
+
+/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain
+ Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRateForSa;
+
+/** Offset 0x02A7 - Thermal Design Current current limit
+ PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
+ Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
+**/
+ UINT16 TdcPowerLimit[5];
+
+/** Offset 0x02B1 - AcLoadline
+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 AcLoadline[5];
+
+/** Offset 0x02BB
+**/
+ UINT8 UnusedUpdSpace8[10];
+
+/** Offset 0x02C5 - DcLoadline
+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
+**/
+ UINT16 DcLoadline[5];
+
+/** Offset 0x02CF - Power State 1 Threshold current
+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi1Threshold[5];
+
+/** Offset 0x02D9 - Power State 2 Threshold current
+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi2Threshold[5];
+
+/** Offset 0x02E3 - Power State 3 Threshold current
+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi3Threshold[5];
+
+/** Offset 0x02ED - Icc Max limit
+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
+**/
+ UINT16 IccMax[5];
+
+/** Offset 0x02F7 - VR Voltage Limit
+ PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
+**/
+ UINT16 VrVoltageLimit[5];
+
+/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. <b>0: False</b>; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisableGt;
+
+/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. <b>0: False</b>; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisableSa;
+
+/** Offset 0x0303 - Enable VR specific mailbox command
+ VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
+ command sent for PS4 exit issue. 11b - Reserved.
+ $EN_DIS
+**/
+ UINT8 SendVrMbxCmd;
+
+/** Offset 0x0304 - Reserved
+ Reserved
+**/
+ UINT8 Reserved2;
+
+/** Offset 0x0305 - Enable or Disable TXT
+ Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 TxtEnable;
+
+/** Offset 0x0306
+**/
+ UINT8 UnusedUpdSpace9[6];
+
+/** Offset 0x030C - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. </b>0: Initialize; <b>1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x030D - McIVR RFI Frequency Prefix
+ PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
+ Minus (-).
+**/
+ UINT8 McivrRfiFrequencyPrefix;
+
+/** Offset 0x030E - McIVR RFI Frequency Adjustment
+ PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
+ increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
+**/
+ UINT8 McivrRfiFrequencyAdjust;
+
+/** Offset 0x030F - FIVR RFI Frequency
+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
+ Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
+ 0-1535 (Up to 153.5MHz) for 19MHz clock.
+**/
+ UINT16 FivrRfiFrequency;
+
+/** Offset 0x0311 - McIVR RFI Spread Spectrum
+ PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
+ 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
+**/
+ UINT8 McivrSpreadSpectrum;
+
+/** Offset 0x0312 - FIVR RFI Spread Spectrum
+ PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
+ Range: 0.0% to 10.0% (0-100).
+**/
+ UINT8 FivrSpreadSpectrum;
+
+/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
+ feature enabled. <b>0: False</b>; 1: True
+ $EN_DIS
+**/
+ UINT8 FastPkgCRampDisableFivr;
+
+/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain
+ Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
+**/
+ UINT8 SlowSlewRateForFivr;
+
+/** Offset 0x0315 - CpuBistData
+ Pointer CPU BIST Data
+**/
+ UINT32 CpuBistData;
+
+/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
+**/
+ UINT8 IslVrCmd;
+
+/** Offset 0x031A - Imon slope1 correction
+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
+**/
+ UINT16 ImonSlope1[5];
+
+/** Offset 0x0324 - CPU VR Power Delivery Design
+ Used to communicate the power delivery design capability of the board. This value
+ is an enum of the available power delivery segments that are defined in the Platform
+ Design Guide.
+**/
+ UINT32 VrPowerDeliveryDesign;
+
+/** Offset 0x0328 - ReservedCpuPostMemProduction
+ Reserved for CPU Post-Mem Production
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemProduction[1];
+
+/** Offset 0x0329
+**/
+ UINT8 UnusedUpdSpace10[29];
+
+/** Offset 0x0346 - Enable DMI ASPM
+ Deprecated.
+ $EN_DIS
+**/
+ UINT8 PchDmiAspm;
+
+/** Offset 0x0347 - Enable Power Optimizer
+ Enable DMI Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 PchPwrOptEnable;
+
+/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble
+ Write or erase is blocked by hardware.
+**/
+ UINT8 PchWriteProtectionEnable[5];
+
+/** Offset 0x034D - PCH Flash Protection Ranges Read Enble
+ Read is blocked by hardware.
+**/
+ UINT8 PchReadProtectionEnable[5];
+
+/** Offset 0x0352 - PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** Offset 0x035C - PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** Offset 0x0366 - Enable Pme
+ Enable Azalia wake-on-ring.
+ $EN_DIS
+**/
+ UINT8 PchHdaPme;
+
+/** Offset 0x0367
+**/
+ UINT8 UnusedUpdSpace11;
+
+/** Offset 0x0368 - VC Type
+ Virtual Channel Type Select: 0: VC0, 1: VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 PchHdaVcType;
+
+/** Offset 0x0369 - HD Audio Link Frequency
+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+ UINT8 PchHdaLinkFrequency;
+
+/** Offset 0x036A - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x036B - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
+ 0: 2T, 1: 1T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
+
+/** Offset 0x036D - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x036E
+**/
+ UINT8 UnusedUpdSpace12[15];
+
+/** Offset 0x037D - Enable PCH Io Apic Entry 24-119
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIoApicEntry24_119;
+
+/** Offset 0x037E - PCH Io Apic ID
+ This member determines IOAPIC ID. Default is 0x02.
+**/
+ UINT8 PchIoApicId;
+
+/** Offset 0x037F
+**/
+ UINT8 UnusedUpdSpace13;
+
+/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshSpiGpioAssign;
+
+/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshUart0GpioAssign;
+
+/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshUart1GpioAssign;
+
+/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshI2c0GpioAssign;
+
+/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshI2c1GpioAssign;
+
+/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshI2c2GpioAssign;
+
+/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp0GpioAssign;
+
+/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp1GpioAssign;
+
+/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp2GpioAssign;
+
+/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp3GpioAssign;
+
+/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp4GpioAssign;
+
+/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp5GpioAssign;
+
+/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp6GpioAssign;
+
+/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIshGp7GpioAssign;
+
+/** Offset 0x038E - PCH ISH PDT Unlock Msg
+ 0: False; 1: True.
+ $EN_DIS
+**/
+ UINT8 PchIshPdtUnlock;
+
+/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchLanLtrEnable;
+
+/** Offset 0x0390
+**/
+ UINT8 UnusedUpdSpace14[3];
+
+/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x0394 - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x0395 - RTC CMOS MEMORY LOCK
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 PchLockDownRtcMemoryLock;
+
+/** Offset 0x0396 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[24];
+
+/** Offset 0x03AE - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 PcieRpPmSci[24];
+
+/** Offset 0x03C6 - Enable PCIE RP Ext Sync
+ Indicate whether the extended synch is enabled.
+**/
+ UINT8 PcieRpExtSync[24];
+
+/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 PcieRpTransmitterHalfSwing[24];
+
+/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[24];
+
+/** Offset 0x040E - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[24];
+
+/** Offset 0x0426 - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 PcieRpUnsupportedRequestReport[24];
+
+/** Offset 0x043E - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpFatalErrorReport[24];
+
+/** Offset 0x0456 - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpNoFatalErrorReport[24];
+
+/** Offset 0x046E - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 PcieRpCorrectableErrorReport[24];
+
+/** Offset 0x0486 - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnFatalError[24];
+
+/** Offset 0x049E - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnNonFatalError[24];
+
+/** Offset 0x04B6 - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnCorrectableError[24];
+
+/** Offset 0x04CE - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[24];
+
+/** Offset 0x04E6
+**/
+ UINT8 UnusedUpdSpace15[24];
+
+/** Offset 0x04FE - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+ PCH_PCIE_SPEED).
+**/
+ UINT8 PcieRpPcieSpeed[24];
+
+/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
+ PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
+ 1: hardware equalization; 4: Fixed Coeficients.
+**/
+ UINT8 PcieRpGen3EqPh3Method[24];
+
+/** Offset 0x052E - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 PcieRpPhysicalSlotNumber[24];
+
+/** Offset 0x0546 - PCIE RP Completion Timeout
+ The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
+**/
+ UINT8 PcieRpCompletionTimeout[24];
+
+/** Offset 0x055E
+**/
+ UINT8 UnusedUpdSpace16[106];
+
+/** Offset 0x05C8 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[24];
+
+/** Offset 0x05E0 - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[24];
+
+/** Offset 0x05F8 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[24];
+
+/** Offset 0x0610 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PcieRpLtrConfigLock[24];
+
+/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm
+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
+**/
+ UINT8 PcieEqPh3LaneParamCm[24];
+
+/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp
+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
+**/
+ UINT8 PcieEqPh3LaneParamCp[24];
+
+/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm
+ PCH_PCIE_EQ_PARAM. Coefficient C-1.
+**/
+ UINT8 PcieSwEqCoeffListCm[5];
+
+/** Offset 0x065D - PCIE Sw Eq CoeffList Cp
+ PCH_PCIE_EQ_PARAM. Coefficient C+1.
+**/
+ UINT8 PcieSwEqCoeffListCp[5];
+
+/** Offset 0x0662 - PCIE Disable RootPort Clock Gating
+ Describes whether the PCI Express Clock Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieDisableRootPortClockGating;
+
+/** Offset 0x0663 - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePeerMemoryWrite;
+
+/** Offset 0x0664
+**/
+ UINT8 UnusedUpdSpace17;
+
+/** Offset 0x0665 - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 PcieComplianceTestMode;
+
+/** Offset 0x0666 - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 PcieRpFunctionSwap;
+
+/** Offset 0x0667
+**/
+ UINT8 UnusedUpdSpace18[2];
+
+/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+ $EN_DIS
+**/
+ UINT8 PchPmPmeB0S5Dis;
+
+/** Offset 0x066A - SPI ChipSelect signal polarity
+ Selects SPI ChipSelect signal polarity.
+**/
+ UINT8 SerialIoSpiCsPolarity[3];
+
+/** Offset 0x066D - PCIE IMR
+ Enables Isolated Memory Region for PCIe.
+ $EN_DIS
+**/
+ UINT8 PcieRpImrEnabled;
+
+/** Offset 0x066E - PCIE IMR port number
+ Selects PCIE root port number for IMR feature.
+**/
+ UINT8 PcieRpImrSelection;
+
+/** Offset 0x066F
+**/
+ UINT8 UnusedUpdSpace19;
+
+/** Offset 0x0670 - PCH Pm Wol Enable Override
+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolEnableOverride;
+
+/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx
+ Determine if enable PCIe to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmPcieWakeFromDeepSx;
+
+/** Offset 0x0672 - PCH Pm WoW lan Enable
+ Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanEnable;
+
+/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable
+ Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
+ PWRM_CFG3 register.
+ $EN_DIS
+**/
+ UINT8 PchPmWoWlanDeepSxEnable;
+
+/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx
+ Determine if enable LAN to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmLanWakeFromDeepSx;
+
+/** Offset 0x0675 - PCH Pm Deep Sx Pol
+ Deep Sx Policy.
+ $EN_DIS
+**/
+ UINT8 PchPmDeepSxPol;
+
+/** Offset 0x0676 - PCH Pm Slp S3 Min Assert
+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+ UINT8 PchPmSlpS3MinAssert;
+
+/** Offset 0x0677 - PCH Pm Slp S4 Min Assert
+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+ UINT8 PchPmSlpS4MinAssert;
+
+/** Offset 0x0678 - PCH Pm Slp Sus Min Assert
+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+ UINT8 PchPmSlpSusMinAssert;
+
+/** Offset 0x0679 - PCH Pm Slp A Min Assert
+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+ UINT8 PchPmSlpAMinAssert;
+
+/** Offset 0x067A - SLP_S0# Override
+ Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
+ will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
+ when debug is enabled. \n
+ Note: This BIOS option should keep 'Auto', other options are intended for advanced
+ configuration only.
+ 0:Disabled, 1:Enabled, 2:Auto
+**/
+ UINT8 SlpS0Override;
+
+/** Offset 0x067B - S0ix Override Settings
+ Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
+ keep PMC default settings. Or select the desired debug probe type for S0ix Override
+ settings.\n
+ Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
+ Note: This BIOS option should keep 'Auto', other options are intended for advanced
+ configuration only.
+ 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
+**/
+ UINT8 SlpS0DisQForDebug;
+
+/** Offset 0x067C - USB Overcurrent Override for DbC
+ This option overrides USB Over Current enablement state that USB OC will be disabled
+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.
+ $EN_DIS
+**/
+ UINT8 PchEnableDbcObs;
+
+/** Offset 0x067D
+**/
+ UINT8 UnusedUpdSpace20[3];
+
+/** Offset 0x0680 - PCH Pm Lpc Clock Run
+ This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
+ Default value is Disabled
+ $EN_DIS
+**/
+ UINT8 PchPmLpcClockRun;
+
+/** Offset 0x0681 - PCH Pm Slp Strch Sus Up
+ Enable SLP_X Stretching After SUS Well Power Up.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpStrchSusUp;
+
+/** Offset 0x0682 - PCH Pm Slp Lan Low Dc
+ Enable/Disable SLP_LAN# Low on DC Power.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpLanLowDc;
+
+/** Offset 0x0683 - PCH Pm Pwr Btn Override Period
+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+ UINT8 PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown
+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableDsxAcPresentPulldown;
+
+/** Offset 0x0685
+**/
+ UINT8 UnusedUpdSpace21;
+
+/** Offset 0x0686 - PCH Pm Disable Native Power Button
+ Power button native mode disable.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableNativePowerButton;
+
+/** Offset 0x0687 - PCH Pm Slp S0 Enable
+ Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpS0Enable;
+
+/** Offset 0x0688 - PCH Pm ME_WAKE_STS
+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmMeWakeSts;
+
+/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS
+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolOvrWkSts;
+
+/** Offset 0x068A - PCH Pm Reset Power Cycle Duration
+ Could be customized in the unit of second. Please refer to EDS for all support settings.
+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+ UINT8 PchPmPwrCycDur;
+
+/** Offset 0x068B - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x068C
+**/
+ UINT8 UnusedUpdSpace22;
+
+/** Offset 0x068D - PCH Sata Pwr Opt Enable
+ SATA Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x068E - PCH Sata eSATA Speed Limit
+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+ $EN_DIS
+**/
+ UINT8 EsataSpeedLimit;
+
+/** Offset 0x068F - PCH Sata Speed Limit
+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
+**/
+ UINT8 SataSpeedLimit;
+
+/** Offset 0x0690 - Enable SATA Port HotPlug
+ Enable SATA Port HotPlug.
+**/
+ UINT8 SataPortsHotPlug[8];
+
+/** Offset 0x0698 - Enable SATA Port Interlock Sw
+ Enable SATA Port Interlock Sw.
+**/
+ UINT8 SataPortsInterlockSw[8];
+
+/** Offset 0x06A0 - Enable SATA Port External
+ Enable SATA Port External.
+**/
+ UINT8 SataPortsExternal[8];
+
+/** Offset 0x06A8 - Enable SATA Port SpinUp
+ Enable the COMRESET initialization Sequence to the device.
+**/
+ UINT8 SataPortsSpinUp[8];
+
+/** Offset 0x06B0 - Enable SATA Port Solid State Drive
+ 0: HDD; 1: SSD.
+**/
+ UINT8 SataPortsSolidStateDrive[8];
+
+/** Offset 0x06B8 - Enable SATA Port Enable Dito Config
+ Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
+**/
+ UINT8 SataPortsEnableDitoConfig[8];
+
+/** Offset 0x06C0 - Enable SATA Port DmVal
+ DITO multiplier. Default is 15.
+**/
+ UINT8 SataPortsDmVal[8];
+
+/** Offset 0x06C8 - Enable SATA Port DmVal
+ DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+ UINT16 SataPortsDitoVal[8];
+
+/** Offset 0x06D8 - Enable SATA Port ZpOdd
+ Support zero power ODD.
+**/
+ UINT8 SataPortsZpOdd[8];
+
+/** Offset 0x06E0 - PCH Sata Rst Raid Device Id
+ Enable RAID Alternate ID.
+ 0:Client, 1:Alternate, 2:Server
+**/
+ UINT8 SataRstRaidDeviceId;
+
+/** Offset 0x06E1 - PCH Sata Rst Raid0
+ RAID0.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid0;
+
+/** Offset 0x06E2 - PCH Sata Rst Raid1
+ RAID1.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid1;
+
+/** Offset 0x06E3 - PCH Sata Rst Raid10
+ RAID10.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid10;
+
+/** Offset 0x06E4 - PCH Sata Rst Raid5
+ RAID5.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid5;
+
+/** Offset 0x06E5 - PCH Sata Rst Irrt
+ Intel Rapid Recovery Technology.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrt;
+
+/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner
+ OROM UI and BANNER.
+ $EN_DIS
+**/
+ UINT8 SataRstOromUiBanner;
+
+/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay
+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
+**/
+ UINT8 SataRstOromUiDelay;
+
+/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock
+ Indicates that the HDD password unlock in the OS is enabled.
+ $EN_DIS
+**/
+ UINT8 SataRstHddUnlock;
+
+/** Offset 0x06E9 - PCH Sata Rst Led Locate
+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
+ enabled on the OS.
+ $EN_DIS
+**/
+ UINT8 SataRstLedLocate;
+
+/** Offset 0x06EA - PCH Sata Rst Irrt Only
+ Allow only IRRT drives to span internal and external ports.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrtOnly;
+
+/** Offset 0x06EB - PCH Sata Rst Smart Storage
+ RST Smart Storage caching Bit.
+ $EN_DIS
+**/
+ UINT8 SataRstSmartStorage;
+
+/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable
+ Enable Intel RST for PCIe Storage remapping.
+**/
+ UINT8 SataRstPcieEnable[3];
+
+/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port
+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
+**/
+ UINT8 SataRstPcieStoragePort[3];
+
+/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+**/
+ UINT8 SataRstPcieDeviceResetDelay[3];
+
+/** Offset 0x06F5 - Enable eMMC HS400 Training
+ Deprecated.
+ $EN_DIS
+**/
+ UINT8 PchScsEmmcHs400TuningRequired;
+
+/** Offset 0x06F6 - Set HS400 Tuning Data Valid
+ Set if HS400 Tuning Data Valid.
+ $EN_DIS
+**/
+ UINT8 PchScsEmmcHs400DllDataValid;
+
+/** Offset 0x06F7 - Rx Strobe Delay Control
+ Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
+**/
+ UINT8 PchScsEmmcHs400RxStrobeDll1;
+
+/** Offset 0x06F8 - Tx Data Delay Control
+ Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
+**/
+ UINT8 PchScsEmmcHs400TxDataDll;
+
+/** Offset 0x06F9 - I/O Driver Strength
+ Deprecated.
+ 0:33 Ohm, 1:40 Ohm, 2:50 Ohm
+**/
+ UINT8 PchScsEmmcHs400DriverStrength;
+
+/** Offset 0x06FA - PCH SerialIo I2C Pads Termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
+ pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
+ for I2C1, and so on.
+**/
+ UINT8 PchSerialIoI2cPadsTermination[6];
+
+/** Offset 0x0700
+**/
+ UINT8 UnusedUpdSpace23;
+
+/** Offset 0x0701 - PcdSerialIoUart0PinMuxing
+ Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
+ 0:default pins, 1:pins muxed with CNV_BRI/RGI
+**/
+ UINT8 SerialIoUart0PinMuxing;
+
+/** Offset 0x0702
+**/
+ UINT8 UnusedUpdSpace24[1];
+
+/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS linesh.
+**/
+ UINT8 SerialIoUartHwFlowCtrl[3];
+
+/** Offset 0x0706 - UART Number For Debug Purpose
+ UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
+ as CNVi BT Core interface, it cannot be used for debug purpose.
+ 0:UART0, 1:UART1, 2:UART2
+**/
+ UINT8 SerialIoDebugUartNumber;
+
+/** Offset 0x0707 - Enable Debug UART Controller
+ Enable debug UART controller after post.
+ $EN_DIS
+**/
+ UINT8 SerialIoEnableDebugUartAfterPost;
+
+/** Offset 0x0708 - Enable Serial IRQ
+ Determines if enable Serial IRQ.
+ $EN_DIS
+**/
+ UINT8 PchSirqEnable;
+
+/** Offset 0x0709 - Serial IRQ Mode Select
+ Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
+ $EN_DIS
+**/
+ UINT8 PchSirqMode;
+
+/** Offset 0x070A - Start Frame Pulse Width
+ Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
+ 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
+**/
+ UINT8 PchStartFramePulse;
+
+/** Offset 0x070B - Reserved
+ Reserved
+ $EN_DIS
+**/
+ UINT8 ReservedForFuture1;
+
+/** Offset 0x070C - Thermal Device SMI Enable
+ This locks down SMI Enable on Alert Thermal Sensor Trip.
+ $EN_DIS
+**/
+ UINT8 PchTsmicLock;
+
+/** Offset 0x070D - Thermal Throttling Custimized T0Level Value
+ Custimized T0Level value.
+**/
+ UINT16 PchT0Level;
+
+/** Offset 0x070F - Thermal Throttling Custimized T1Level Value
+ Custimized T1Level value.
+**/
+ UINT16 PchT1Level;
+
+/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value
+ Custimized T2Level value.
+**/
+ UINT16 PchT2Level;
+
+/** Offset 0x0713 - Enable The Thermal Throttle
+ Enable the thermal throttle function.
+ $EN_DIS
+**/
+ UINT8 PchTTEnable;
+
+/** Offset 0x0714 - PMSync State 13
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+ at least T2 state.
+ $EN_DIS
+**/
+ UINT8 PchTTState13Enable;
+
+/** Offset 0x0715 - Thermal Throttle Lock
+ Thermal Throttle Lock.
+ $EN_DIS
+**/
+ UINT8 PchTTLock;
+
+/** Offset 0x0716 - Thermal Throttling Suggested Setting
+ Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 TTSuggestedSetting;
+
+/** Offset 0x0717 - Enable PCH Cross Throttling
+ Enable/Disable PCH Cross Throttling
+ $EN_DIS
+**/
+ UINT8 TTCrossThrottling;
+
+/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable
+ DMI Thermal Sensor Autonomous Width Enable.
+ $EN_DIS
+**/
+ UINT8 PchDmiTsawEn;
+
+/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting
+ DMT thermal sensor suggested representative values.
+ $EN_DIS
+**/
+ UINT8 DmiSuggestedSetting;
+
+/** Offset 0x071A - Thermal Sensor 0 Target Width
+ DMT thermal sensor suggested representative values.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS0TW;
+
+/** Offset 0x071B - Thermal Sensor 1 Target Width
+ Thermal Sensor 1 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS1TW;
+
+/** Offset 0x071C - Thermal Sensor 2 Target Width
+ Thermal Sensor 2 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS2TW;
+
+/** Offset 0x071D - Thermal Sensor 3 Target Width
+ Thermal Sensor 3 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS3TW;
+
+/** Offset 0x071E - Port 0 T1 Multipler
+ Port 0 T1 Multipler.
+**/
+ UINT8 SataP0T1M;
+
+/** Offset 0x071F - Port 0 T2 Multipler
+ Port 0 T2 Multipler.
+**/
+ UINT8 SataP0T2M;
+
+/** Offset 0x0720 - Port 0 T3 Multipler
+ Port 0 T3 Multipler.
+**/
+ UINT8 SataP0T3M;
+
+/** Offset 0x0721 - Port 0 Tdispatch
+ Port 0 Tdispatch.
+**/
+ UINT8 SataP0TDisp;
+
+/** Offset 0x0722 - Port 1 T1 Multipler
+ Port 1 T1 Multipler.
+**/
+ UINT8 SataP1T1M;
+
+/** Offset 0x0723 - Port 1 T2 Multipler
+ Port 1 T2 Multipler.
+**/
+ UINT8 SataP1T2M;
+
+/** Offset 0x0724 - Port 1 T3 Multipler
+ Port 1 T3 Multipler.
+**/
+ UINT8 SataP1T3M;
+
+/** Offset 0x0725 - Port 1 Tdispatch
+ Port 1 Tdispatch.
+**/
+ UINT8 SataP1TDisp;
+
+/** Offset 0x0726 - Port 0 Tinactive
+ Port 0 Tinactive.
+**/
+ UINT8 SataP0Tinact;
+
+/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch
+ Port 0 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP0TDispFinit;
+
+/** Offset 0x0728 - Port 1 Tinactive
+ Port 1 Tinactive.
+**/
+ UINT8 SataP1Tinact;
+
+/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch
+ Port 1 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP1TDispFinit;
+
+/** Offset 0x072A - Sata Thermal Throttling Suggested Setting
+ Sata Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 SataThermalSuggestedSetting;
+
+/** Offset 0x072B - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+ $EN_DIS
+**/
+ UINT8 PchMemoryThrottlingEnable;
+
+/** Offset 0x072C - Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPmsyncEnable[2];
+
+/** Offset 0x072E - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryC0TransmitEnable[2];
+
+/** Offset 0x0730 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPinSelection[2];
+
+/** Offset 0x0732 - Thermal Device Temperature
+ Decides the temperature.
+**/
+ UINT16 PchTemperatureHotLevel;
+
+/** Offset 0x0734 - Enable xHCI Compliance Mode
+ Compliance Mode can be enabled for testing through this option but this is disabled
+ by default.
+ $EN_DIS
+**/
+ UINT8 PchEnableComplianceMode;
+
+/** Offset 0x0735 - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x0745 - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x074F - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x0750 - PCH Sata Rst Optane Memory
+ Optane Memory
+ $EN_DIS
+**/
+ UINT8 SataRstOptaneMemory;
+
+/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage
+ CPU Attached Storage
+ $EN_DIS
+**/
+ UINT8 SataRstCpuAttachedStorage;
+
+/** Offset 0x0752
+**/
+ UINT8 UnusedUpdSpace25[2];
+
+/** Offset 0x0754 - Pch PCIE device override table pointer
+ The PCIe device table is being used to override PCIe device ASPM settings. This
+ is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
+ refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
+ must be 0.
+**/
+ UINT32 PchPcieDeviceOverrideTablePtr;
+
+/** Offset 0x0758 - Enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+ emulation must be enabled, and WDAT table must not be exposed to the OS.
+ $EN_DIS
+**/
+ UINT8 EnableTcoTimer;
+
+/** Offset 0x0759 - BgpdtHash[4]
+ BgpdtHash values
+**/
+ UINT64 BgpdtHash[4];
+
+/** Offset 0x0779 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
+
+/** Offset 0x077D - BiosGuardModulePtr
+ BiosGuardModulePtr default values
+**/
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0785 - SendEcCmd
+ SendEcCmd function pointer. \n
+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
+**/
+ UINT64 SendEcCmd;
+
+/** Offset 0x078D - EcCmdProvisionEav
+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+**/
+ UINT8 EcCmdProvisionEav;
+
+/** Offset 0x078E - EcCmdLock
+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+**/
+ UINT8 EcCmdLock;
+
+/** Offset 0x078F - SgxEpoch0
+ SgxEpoch0 default values
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0797 - SgxEpoch1
+ SgxEpoch1 default values
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x079F - SgxSinitNvsData
+ SgxSinitNvsData default values
+**/
+ UINT8 SgxSinitNvsData;
+
+/** Offset 0x07A0 - Si Config CSM Flag.
+ Platform specific common policies that used by several silicon components. CSM status flag.
+ $EN_DIS
+**/
+ UINT8 SiCsmFlag;
+
+/** Offset 0x07A1
+**/
+ UINT32 SiSsidTablePtr;
+
+/** Offset 0x07A5
+**/
+ UINT16 SiNumberOfSsidTableEntry;
+
+/** Offset 0x07A7 - SATA RST Interrupt Mode
+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
+ 0:Msix, 1:Msi, 2:Legacy
+**/
+ UINT8 SataRstInterrupt;
+
+/** Offset 0x07A8 - ME Unconfig on RTC clear
+ 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
+ 2: Cmos is clear, status unkonwn. 3: Reserved
+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+ is clear, 3: Reserved
+**/
+ UINT8 MeUnconfigOnRtcClear;
+
+/** Offset 0x07A9 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable
+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+ and VccSTG rails instead of SLP_S0# pin.
+ $EN_DIS
+**/
+ UINT8 PmcCpuC10GatePinEnable;
+
+/** Offset 0x07AB - Pch Dmi Aspm Ctrl
+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
+**/
+ UINT8 PchDmiAspmCtrl;
+
+/** Offset 0x07AC
+**/
+ UINT8 ReservedFspsUpd[1];
+} FSP_S_CONFIG;
+
+/** Fsp S Test Configuration
+**/
+typedef struct {
+
+/** Offset 0x07AD
+**/
+ UINT32 Signature;
+
+/** Offset 0x07B1 - Enable/Disable Device 7
+ Enable: Device 7 enabled, Disable (Default): Device 7 disabled
+ $EN_DIS
+**/
+ UINT8 ChapDeviceEnable;
+
+/** Offset 0x07B2 - Skip PAM register lock
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ $EN_DIS
+**/
+ UINT8 SkipPamLock;
+
+/** Offset 0x07B3 - EDRAM Test Mode
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
+**/
+ UINT8 EdramTestMode;
+
+/** Offset 0x07B4 - DMI Extended Sync Control
+ Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
+ Sync Control
+ $EN_DIS
+**/
+ UINT8 DmiExtSync;
+
+/** Offset 0x07B5 - DMI IOT Control
+ Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
+ $EN_DIS
+**/
+ UINT8 DmiIot;
+
+/** Offset 0x07B6 - PEG Max Payload size per root port
+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
+ 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
+**/
+ UINT8 PegMaxPayload[4];
+
+/** Offset 0x07BA - Enable/Disable IGFX RenderStandby
+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+ $EN_DIS
+**/
+ UINT8 RenderStandby;
+
+/** Offset 0x07BB - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x07BC - Enable/Disable CdynmaxClamp
+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
+ $EN_DIS
+**/
+ UINT8 CdynmaxClampEnable;
+
+/** Offset 0x07BD - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x07BE - GT Frequency Limit
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+**/
+ UINT8 GtFreqMax;
+
+/** Offset 0x07BF - Disable Turbo GT
+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
+ $EN_DIS
+**/
+ UINT8 DisableTurboGt;
+
+/** Offset 0x07C0 - SaPostMemTestRsvd
+ Reserved for SA Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 SaPostMemTestRsvd[11];
+
+/** Offset 0x07CB - 1-Core Ratio Limit
+ 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
+ to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,
+ 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83
+**/
+ UINT8 OneCoreRatioLimit;
+
+/** Offset 0x07CC - 2-Core Ratio Limit
+ 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 TwoCoreRatioLimit;
+
+/** Offset 0x07CD - 3-Core Ratio Limit
+ 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 ThreeCoreRatioLimit;
+
+/** Offset 0x07CE - 4-Core Ratio Limit
+ 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 FourCoreRatioLimit;
+
+/** Offset 0x07CF - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x07D0 - Hardware Duty Cycle Control
+ Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 HdcControl;
+
+/** Offset 0x07D1 - Package Long duration turbo mode time
+ Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
+ 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PowerLimit1Time;
+
+/** Offset 0x07D2 - Short Duration Turbo Mode
+ Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PowerLimit2;
+
+/** Offset 0x07D3 - Turbo settings Lock
+ Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 TurboPowerLimitLock;
+
+/** Offset 0x07D4 - Package PL3 time window
+ Package PL3 time window range for this policy from 0 to 64ms
+**/
+ UINT8 PowerLimit3Time;
+
+/** Offset 0x07D5 - Package PL3 Duty Cycle
+ Package PL3 Duty Cycle; Valid Range is 0 to 100
+**/
+ UINT8 PowerLimit3DutyCycle;
+
+/** Offset 0x07D6 - Package PL3 Lock
+ Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit3Lock;
+
+/** Offset 0x07D7 - Package PL4 Lock
+ Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit4Lock;
+
+/** Offset 0x07D8 - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>,
+ For all other SKUs the recommended default are <b>0</b>
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable
+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
+ below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
+ For all other SKUs the recommended default are <b>0: Disabled</b>.
+ $EN_DIS
+**/
+ UINT8 TccOffsetClamp;
+
+/** Offset 0x07DA - Tcc Offset Lock
+ Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
+ target; 0: Disabled; <b>1: Enabled </b>.
+ $EN_DIS
+**/
+ UINT8 TccOffsetLock;
+
+/** Offset 0x07DB - Custom Ratio State Entries
+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+ ratio table.Sets the number of custom P-states. At least 2 states must be present
+**/
+ UINT8 NumberOfEntries;
+
+/** Offset 0x07DC - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
+**/
+ UINT8 Custom1PowerLimit1Time;
+
+/** Offset 0x07DD - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
+**/
+ UINT8 Custom1TurboActivationRatio;
+
+/** Offset 0x07DE - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom1ConfigTdpControl;
+
+/** Offset 0x07DF - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
+**/
+ UINT8 Custom2PowerLimit1Time;
+
+/** Offset 0x07E0 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
+**/
+ UINT8 Custom2TurboActivationRatio;
+
+/** Offset 0x07E1 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom2ConfigTdpControl;
+
+/** Offset 0x07E2 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
+**/
+ UINT8 Custom3PowerLimit1Time;
+
+/** Offset 0x07E3 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
+**/
+ UINT8 Custom3TurboActivationRatio;
+
+/** Offset 0x07E4 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom3ConfigTdpControl;
+
+/** Offset 0x07E5 - ConfigTdp mode settings Lock
+ Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ConfigTdpLock;
+
+/** Offset 0x07E6 - Load Configurable TDP SSDT
+ Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ConfigTdpBios;
+
+/** Offset 0x07E7 - PL1 Enable value
+ PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit1;
+
+/** Offset 0x07E8 - PL1 timewindow
+ PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
+ , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PsysPowerLimit1Time;
+
+/** Offset 0x07E9 - PL2 Enable Value
+ PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit2;
+
+/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher
+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MlcStreamerPrefetcher;
+
+/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher
+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 MlcSpatialPrefetcher;
+
+/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions
+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x07ED - Enable or Disable initialization of machine check registers
+ Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MachineCheckEnable;
+
+/** Offset 0x07EE - Enable or Disable processor debug features
+ Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceEnable;
+
+/** Offset 0x07EF - Lock or Unlock debug interface features
+ Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceLockEnable;
+
+/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI
+ AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop
+**/
+ UINT8 ApIdleManner;
+
+/** Offset 0x07F1 - Control on Processor Trace output scheme
+ Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+ 0: Single Range Output, 1: ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x07F2 - Enable or Disable Processor Trace feature
+ Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x07F3 - Base of memory region allocated for Processor Trace
+ Base address of memory region allocated for Processor Trace. Processor Trace requires
+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT64 ProcessorTraceMemBase;
+
+/** Offset 0x07FB - Memory region allocation for Processor Trace
+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT32 ProcessorTraceMemLength;
+
+/** Offset 0x07FF - Enable or Disable Voltage Optimization feature
+ Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 VoltageOptimization;
+
+/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology
+ Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x0801 - Enable or Disable Energy Efficient P-state
+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
+ <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientPState;
+
+/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo
+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
+ <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientTurbo;
+
+/** Offset 0x0803 - Enable or Disable T states
+ Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TStates;
+
+/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 BiProcHot;
+
+/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally
+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DisableProcHotOut;
+
+/** Offset 0x0806 - Enable or Disable PROCHOT# Response
+ Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcHotResponse;
+
+/** Offset 0x0807 - Enable or Disable VR Thermal Alert
+ Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableVrThermalAlert;
+
+/** Offset 0x0808 - Enable or Disable Thermal Reporting
+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 AutoThermalReporting;
+
+/** Offset 0x0809 - Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 ThermalMonitor;
+
+/** Offset 0x080A - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x080B - Configure C-State Configuration Lock
+ Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 PmgCstCfgCtrlLock;
+
+/** Offset 0x080C - Enable or Disable Enhanced C-states
+ Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x080D - Enable or Disable Package Cstate Demotion
+ Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
+ Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x080F - Enable or Disable CState-Pre wake
+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 CStatePreWake;
+
+/** Offset 0x0810 - Enable or Disable TimedMwait Support.
+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 TimedMwait;
+
+/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection
+ Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CstCfgCtrIoMwaitRedirection;
+
+/** Offset 0x0812 - Set the Max Pkg Cstate
+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x0813 - TimeUnit for C-State Latency Control0
+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl0TimeUnit;
+
+/** Offset 0x0814 - TimeUnit for C-State Latency Control1
+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl1TimeUnit;
+
+/** Offset 0x0815 - TimeUnit for C-State Latency Control2
+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl2TimeUnit;
+
+/** Offset 0x0816 - TimeUnit for C-State Latency Control3
+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl3TimeUnit;
+
+/** Offset 0x0817 - TimeUnit for C-State Latency Control4
+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl4TimeUnit;
+
+/** Offset 0x0818 - TimeUnit for C-State Latency Control5
+ TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl5TimeUnit;
+
+/** Offset 0x0819 - Interrupt Redirection Mode Select
+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
+**/
+ UINT8 PpmIrmSetting;
+
+/** Offset 0x081A - Lock prochot configuration
+ Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ProcHotLock;
+
+/** Offset 0x081B - Configuration for boot TDP selection
+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
+ Up;0xFF : Deactivate
+**/
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x081C - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+ through MSR 1FC bit 20)Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x081D - Max P-State Ratio
+ Max P-State Ratio, Valid Range 0 to 0x7F
+**/
+ UINT8 MaxRatio;
+
+/** Offset 0x081E - P-state ratios for custom P-state table
+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+ are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatio[40];
+
+/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table
+ P-state ratios for max 16 version of custom P-state table. This table is used for
+ OS versions limited to a max of 16 P-States. If the first entry of this table is
+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
+ of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatioMax16[16];
+
+/** Offset 0x0856 - Platform Power Pmax
+ PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
+ Range 0-1024 Watts. Value of 800 = 100W
+**/
+ UINT16 PsysPmax;
+
+/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl0Irtl;
+
+/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl1Irtl;
+
+/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2
+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl2Irtl;
+
+/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3
+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl3Irtl;
+
+/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4
+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl4Irtl;
+
+/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5
+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
+**/
+ UINT16 CstateLatencyControl5Irtl;
+
+/** Offset 0x0864 - Package Long duration turbo mode power limit
+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ Valid Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit1;
+
+/** Offset 0x0868 - Package Short duration turbo mode power limit
+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit2Power;
+
+/** Offset 0x086C - Package PL3 power limit
+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit3;
+
+/** Offset 0x0870 - Package PL4 power limit
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit4;
+
+/** Offset 0x0874 - Tcc Offset Time Window for RATL
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 TccOffsetTimeWindowForRatl;
+
+/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1
+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit1;
+
+/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1
+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit2;
+
+/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2
+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit1;
+
+/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2
+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit2;
+
+/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3
+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit1;
+
+/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3
+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit2;
+
+/** Offset 0x0890 - Platform PL1 power
+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit1Power;
+
+/** Offset 0x0894 - Platform PL2 power
+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit2Power;
+
+/** Offset 0x0898 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents Three
+ Strike counter from incrementing; <b>0: False</b>; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 HwpInterruptControl;
+
+/** Offset 0x089A - 5-Core Ratio Limit
+ 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 FiveCoreRatioLimit;
+
+/** Offset 0x089B - 6-Core Ratio Limit
+ 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SixCoreRatioLimit;
+
+/** Offset 0x089C - 7-Core Ratio Limit
+ 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SevenCoreRatioLimit;
+
+/** Offset 0x089D - 8-Core Ratio Limit
+ 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 EightCoreRatioLimit;
+
+/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0
+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
+ $EN_DIS
+**/
+ UINT8 EnableItbm;
+
+/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver
+ Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 EnableItbmDriver;
+
+/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion
+ Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateAutoDemotion;
+
+/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion
+ Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateUnDemotion;
+
+/** Offset 0x08A2 - CpuWakeUpTimer
+ Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
+ to 180 seconds. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 CpuWakeUpTimer;
+
+/** Offset 0x08A3 - Minimum Ring ratio limit override
+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MinRingRatioLimit;
+
+/** Offset 0x08A4 - Minimum Ring ratio limit override
+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MaxRingRatioLimit;
+
+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C3StateAutoDemotion;
+
+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C3StateUnDemotion;
+
+/** Offset 0x08A7 - ReservedCpuPostMemTest
+ Reserved for CPU Post-Mem Test
+ $EN_DIS
+**/
+ UINT8 ReservedCpuPostMemTest[19];
+
+/** Offset 0x08BA - SgxSinitDataFromTpm
+ SgxSinitDataFromTpm default values
+**/
+ UINT8 SgxSinitDataFromTpm;
+
+/** Offset 0x08BB - End of Post message
+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+ UINT8 EndOfPostMessage;
+
+/** Offset 0x08BC - D0I3 Setting for HECI Disable
+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+ HECI devices
+ $EN_DIS
+**/
+ UINT8 DisableD0I3SettingForHeci;
+
+/** Offset 0x08BD - HD Audio Reset Wait Timer
+ The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
+**/
+ UINT16 PchHdaResetWaitTimer;
+
+/** Offset 0x08BF - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x08C1 - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x08C2 - PCH Unlock SBI access
+ Deprecated
+ $EN_DIS
+**/
+ UINT8 PchSbiUnlock;
+
+/** Offset 0x08C3 - PCH Unlock SideBand access
+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+ $EN_DIS
+**/
+ UINT8 PchSbAccessUnlock;
+
+/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[24];
+
+/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0954 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
+
+/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale
+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+ UINT8 PcieRpSlotPowerLimitScale[24];
+
+/** Offset 0x09FC - PCIE RP Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+ UINT16 PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
+**/
+ UINT8 PcieRpUptp[24];
+
+/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset
+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
+**/
+ UINT8 PcieRpDptp[24];
+
+/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode
+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePort8xhDecode;
+
+/** Offset 0x0A5D - PCIE Port8xh Decode Port Index
+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
+**/
+ UINT8 PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0A5E - PCH Energy Reporting
+ Disable/Enable PCH to CPU energy report feature.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableEnergyReport;
+
+/** Offset 0x0A5F - PCH Sata Test Mode
+ Allow entrance to the PCH SATA test modes.
+ $EN_DIS
+**/
+ UINT8 SataTestMode;
+
+/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable
+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+ $EN_DIS
+**/
+ UINT8 PchXhciOcLock;
+
+/** Offset 0x0A61
+**/
+ UINT8 UnusedUpdSpace26[17];
+
+/** Offset 0x0A72 - Skip POSTBOOT SAI
+ Deprecated
+ $EN_DIS
+**/
+ UINT8 SkipPostBootSai;
+
+/** Offset 0x0A73 - Mctp Broadcast Cycle
+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MctpBroadcastCycle;
+
+/** Offset 0x0A74
+**/
+ UINT8 ReservedFspsTestUpd[12];
+} FSP_S_TEST_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x07AD
+**/
+ FSP_S_TEST_CONFIG FspsTestConfig;
+
+/** Offset 0x0A80
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h
new file mode 100644
index 0000000..eeba7ae
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h
@@ -0,0 +1,136 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionSize;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved[16];
+} FSPT_CORE_UPD;
+
+/** Fsp T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - PcdSerialIoUartDebugEnable
+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+**/
+ UINT8 PcdSerialIoUartDebugEnable;
+
+/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 PcdSerialIoUartNumber;
+
+/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
+ Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
+ set to UART0.
+ 0:default pins, 1:pins muxed with CNV_BRI/RGI
+**/
+ UINT8 PcdSerialIoUart0PinMuxing;
+
+/** Offset 0x0043
+**/
+ UINT8 UnusedUpdSpace0;
+
+/** Offset 0x0044
+**/
+ UINT32 PcdSerialIoUartInputClock;
+
+/** Offset 0x0048 - Pci Express Base Address
+ Base address to be programmed for Pci Express
+**/
+ UINT64 PcdPciExpressBaseAddress;
+
+/** Offset 0x0050 - Pci Express Region Length
+ Region Length to be programmed for Pci Express
+**/
+ UINT32 PcdPciExpressRegionLength;
+
+/** Offset 0x0054
+**/
+ UINT8 ReservedFsptUpd1[44];
+} FSP_T_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+ FSP_T_CONFIG FsptConfig;
+
+/** Offset 0x0080
+**/
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
new file mode 100644
index 0000000..e2a3e09
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
@@ -0,0 +1,288 @@
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ at copyright
+ INTEL CONFIDENTIAL
+ Copyright 1999 - 2018 Intel Corporation.
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
+
+ at par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef bmCold
+#define bmCold 0 // Cold boot
+#endif
+#ifndef bmWarm
+#define bmWarm 1 // Warm boot
+#endif
+#ifndef bmS3
+#define bmS3 2 // S3 resume
+#endif
+#ifndef bmFast
+#define bmFast 3 // Fast boot
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef CPU_CFL//CNL
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#else//CFL
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 3
+#endif
+#endif//CPU_CFL-endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+typedef struct {
+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
+} MRC_TA_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT32 PrmrrBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+#ifdef CPU_CFL
+ UINT32 GdxcIotBase;
+ UINT32 GdxcIotSize;
+ UINT32 GdxcMotBase;
+ UINT32 GdxcMotSize;
+#endif //CPU_CFL
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
--
To view, visit https://review.coreboot.org/25335
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f
Gerrit-Change-Number: 25335
Gerrit-PatchSet: 1
Gerrit-Owner: Kin Wai Ng <kin.wai.ng at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180323/6dd381a8/attachment-0001.html>
More information about the coreboot-gerrit
mailing list