<p>Kin Wai Ng has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25335">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD Headers<br><br>Header files based on FSP 7.0.25.34<br><br>BUG=none<br>BRANCH=none<br>TEST=built coreboot without build error.<br><br>Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h<br>6 files changed, 6,586 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/25335/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h</span><br><span>new file mode 100644</span><br><span>index 0000000..fca01e9</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h</span><br><span>@@ -0,0 +1,67 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file
</span><br><span style="color: hsl(120, 100%, 40%);">+ Header file for Firmware Version Information
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ This program and the accompanying materials are licensed and made available under
</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms and conditions of the BSD License which accompanies this distribution.
</span><br><span style="color: hsl(120, 100%, 40%);">+ The full text of the license may be found at
</span><br><span style="color: hsl(120, 100%, 40%);">+ http://opensource.org/licenses/bsd-license.php
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
</span><br><span style="color: hsl(120, 100%, 40%);">+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+#define _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MajorVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MinorVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BuildNumber;
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
</span><br><span style="color: hsl(120, 100%, 40%);">+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SMBIOS_STANDARD_H__
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The Smbios structure header.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Type;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Length;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Handle;
</span><br><span style="color: hsl(120, 100%, 40%);">+} SMBIOS_STRUCTURE;
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information HOB Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
</span><br><span style="color: hsl(120, 100%, 40%);">+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..ae25814</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h</span><br><span>@@ -0,0 +1,48 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspEas.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..a147f4f</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>@@ -0,0 +1,2804 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPMUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPMUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <MemInfoHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision; ///< Chipset Init Info Revision
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rsvd[3]; ///< Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
</span><br><span style="color: hsl(120, 100%, 40%);">+} CHIPSET_INIT_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040 - Platform Reserved Memory Size</span><br><span style="color: hsl(120, 100%, 40%);">+ The minimum platform memory size required to pass control into DXE</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 PlatformMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MemorySpdPtr01;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MemorySpdPtr10;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MemorySpdPtr11;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0058 - SPD Data Length</span><br><span style="color: hsl(120, 100%, 40%);">+ Length of SPD Data</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x100:256 Bytes, 0x200:512 Bytes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MemorySpdDataLen;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x005A - Dq Byte Map CH0</span><br><span style="color: hsl(120, 100%, 40%);">+ Dq byte mapping between CPU and DRAM, Channel 0: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DqByteMapCh0[12];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0066 - Dq Byte Map CH1</span><br><span style="color: hsl(120, 100%, 40%);">+ Dq byte mapping between CPU and DRAM, Channel 1: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DqByteMapCh1[12];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DqsMapCpu2DramCh0[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x007A - Dqs Map CPU to DRAM CH 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DqsMapCpu2DramCh1[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0082 - RcompResister settings</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design</span><br><span style="color: hsl(120, 100%, 40%);">+ Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide</span><br><span style="color: hsl(120, 100%, 40%);">+ the appropriate values.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RcompResistor[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0088 - RcompTarget settings</span><br><span style="color: hsl(120, 100%, 40%);">+ RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RcompTarget[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0092 - Dqs Pins Interleaved Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates DqPinsInterleaved setting: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DqPinsInterleaved;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0093 - VREF_CA</span><br><span style="color: hsl(120, 100%, 40%);">+ CA Vref routing: board-dependent</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2:VREF_CA to CH_A and VREF_DQ_B to CH_B</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CaVrefConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0094 - Smram Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ The SMM Regions AB-SEG and/or H-SEG reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SmramMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0095 - MRC Fast Boot</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable the MRC fast path thru the MRC</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MrcFastBoot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0096 - Rank Margin Tool per Task</span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables the user to execute Rank Margin Tool per major training step</span><br><span style="color: hsl(120, 100%, 40%);">+ in the MRC.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RmtPerTask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0097 - Training Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables the trained state tracing feature in MRC. This feature will</span><br><span style="color: hsl(120, 100%, 40%);">+ print out the key training parameters state across major training steps.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TrainTrace;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0098 - Intel Enhanced Debug</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 : Disable, 0x400000 : Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 IedSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x009C - Tseg Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0400000:4MB, 0x01000000:16MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A0 - MMIO Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MmioSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A2 - Probeless Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.</span><br><span style="color: hsl(120, 100%, 40%);">+ This also requires IED to be enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProbelessTrace;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A3 - GDXC IOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcIotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A4 - GDXC MOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcMotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A5 - Enable SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SMBus controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SmbusEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A6 - Spd Address Tabl</span><br><span style="color: hsl(120, 100%, 40%);">+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used</span><br><span style="color: hsl(120, 100%, 40%);">+ if SPD Address is 00</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdAddressTable[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AA - Platform Debug Consent</span><br><span style="color: hsl(120, 100%, 40%);">+ To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.</span><br><span style="color: hsl(120, 100%, 40%);">+ Enabling this BIOS option may alter the default value of other debug-related BIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]</span><br><span style="color: hsl(120, 100%, 40%);">+ have the same setting</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),</span><br><span style="color: hsl(120, 100%, 40%);">+ 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PlatformDebugConsent;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support</span><br><span style="color: hsl(120, 100%, 40%);">+ This BIOS option enables kernel and platform debug for USB3 interface over a UFP</span><br><span style="color: hsl(120, 100%, 40%);">+ Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:Enabled, 2:No Change</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DciUsb3TypecUfpDbg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AC - PCH Trace Hub Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'</span><br><span style="color: hsl(120, 100%, 40%);">+ if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTraceHubMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,</span><br><span style="color: hsl(120, 100%, 40%);">+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTraceHubMemReg0Size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,</span><br><span style="color: hsl(120, 100%, 40%);">+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTraceHubMemReg1Size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00AF - PchPreMemRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for PCH Pre-Mem Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPreMemRsvd[9];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of memory preallocated for internal graphics.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00:0 MB, 0x01:32 MB, 0x02:64 MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IgdDvmt50PreAlloc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00B9 - Internal Graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable internal graphics.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 InternalGfx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00BA - Aperture Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Select the Aperture Size.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:128 MB, 1:256 MB, 2:512 MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ApertureSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00BB - Board Type</span><br><span style="color: hsl(120, 100%, 40%);">+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile</span><br><span style="color: hsl(120, 100%, 40%);">+ Halo, 7=UP Server</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UserBd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00BC - SA GV</span><br><span style="color: hsl(120, 100%, 40%);">+ System Agent dynamic frequency support and when enabled memory will be training</span><br><span style="color: hsl(120, 100%, 40%);">+ at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2=FixedHigh, and 3=Enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaGv;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00BD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00BE - DDR Frequency Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,</span><br><span style="color: hsl(120, 100%, 40%);">+ i.e. divide by 133 or 100</span><br><span style="color: hsl(120, 100%, 40%);">+ 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DdrFreqLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C0 - Low Frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2400, 2667, 2933 and 0 for Auto.</span><br><span style="color: hsl(120, 100%, 40%);">+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 FreqSaGvLow;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C2 - Mid Frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2400, 2667, 2933 and 0 for Auto.</span><br><span style="color: hsl(120, 100%, 40%);">+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 FreqSaGvMid;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C4 - Rank Margin Tool</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Rank Margin Tool.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RMT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C5 - Channel A DIMM Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableDimmChannel0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C6 - Channel B DIMM Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableDimmChannel1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C7 - Scrambler Support</span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables data scrambling in memory.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScramblerSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00D8 - SPD Profile Selected</span><br><span style="color: hsl(120, 100%, 40%);">+ Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP</span><br><span style="color: hsl(120, 100%, 40%);">+ Profile 1, 3=XMP Profile 2</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdProfileSelected;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00D9 - Memory Reference Clock</span><br><span style="color: hsl(120, 100%, 40%);">+ 100MHz, 133MHz.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:133MHz, 1:100MHz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RefClk;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DA - Memory Voltage</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Voltage Override (Vddq). Default = no override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40</span><br><span style="color: hsl(120, 100%, 40%);">+ Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 VddVoltage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DC - Memory Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to</span><br><span style="color: hsl(120, 100%, 40%);">+ recalculate memory timings listed below.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ratio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DD - QCLK Odd Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Adds 133 or 100 MHz to QCLK frequency, depending on RefClk</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 OddRatioMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DE - tCL</span><br><span style="color: hsl(120, 100%, 40%);">+ CAS Latency, 0: AUTO, max: 31</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tCL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DF - tCWL</span><br><span style="color: hsl(120, 100%, 40%);">+ Min CAS Write Latency Delay Time, 0: AUTO, max: 34</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tCWL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E0 - tRCD/tRP</span><br><span style="color: hsl(120, 100%, 40%);">+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRCDtRP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E1 - tRRD</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 15</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRRD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E2 - tFAW</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Four Activate Window Delay Time, 0: AUTO, max: 63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tFAW;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E4 - tRAS</span><br><span style="color: hsl(120, 100%, 40%);">+ RAS Active Time, 0: AUTO, max: 64</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRAS;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E6 - tREFI</span><br><span style="color: hsl(120, 100%, 40%);">+ Refresh Interval, 0: AUTO, max: 65535</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tREFI;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E8 - tRFC</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Refresh Recovery Delay Time, 0: AUTO, max: 1023</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00EA - tRTP</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal</span><br><span style="color: hsl(120, 100%, 40%);">+ values: 5, 6, 7, 8, 9, 10, 12</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRTP;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00EB - tWR</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,</span><br><span style="color: hsl(120, 100%, 40%);">+ 20, 24, 30, 34, 40</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,</span><br><span style="color: hsl(120, 100%, 40%);">+ 34:34, 40:40</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00EC - tWTR</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWTR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00ED - NMode</span><br><span style="color: hsl(120, 100%, 40%);">+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 NModeSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00EE - DllBwEn[0]</span><br><span style="color: hsl(120, 100%, 40%);">+ DllBwEn[0], for 1067 (0..7)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DllBwEn0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00EF - DllBwEn[1]</span><br><span style="color: hsl(120, 100%, 40%);">+ DllBwEn[1], for 1333 (0..7)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DllBwEn1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F0 - DllBwEn[2]</span><br><span style="color: hsl(120, 100%, 40%);">+ DllBwEn[2], for 1600 (0..7)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DllBwEn2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F1 - DllBwEn[3]</span><br><span style="color: hsl(120, 100%, 40%);">+ DllBwEn[3], for 1867 and up (0..7)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DllBwEn3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F2 - ISVT IO Port Address</span><br><span style="color: hsl(120, 100%, 40%);">+ ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IsvtIoPort;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F3 - CPU Trace Hub Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'</span><br><span style="color: hsl(120, 100%, 40%);">+ trace hub functionality.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1:Target Debugger Mode</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuTraceHubMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F4 - CPU Trace Hub Memory Region 0</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,</span><br><span style="color: hsl(120, 100%, 40%);">+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuTraceHubMemReg0Size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F5 - CPU Trace Hub Memory Region 1</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,</span><br><span style="color: hsl(120, 100%, 40%);">+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuTraceHubMemReg1Size;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeciC10Reset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeciSxReset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace2[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FC - Enable Intel HD Audio (Azalia)</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1: Enable (Default) Azalia controller</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FD - Enable PCH ISH Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1: Enable (Default) ISH Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FE - HECI Timeouts</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1: Enable (Default) timeout check for HECI</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HeciTimeouts;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0100 - HECI1 BAR address</span><br><span style="color: hsl(120, 100%, 40%);">+ BAR address of HECI1</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Heci1BarAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0104 - HECI2 BAR address</span><br><span style="color: hsl(120, 100%, 40%);">+ BAR address of HECI2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Heci2BarAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0108 - HECI3 BAR address</span><br><span style="color: hsl(120, 100%, 40%);">+ BAR address of HECI3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Heci3BarAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x010C - SG dGPU Power Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is</span><br><span style="color: hsl(120, 100%, 40%);">+ 300=300 microseconds</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SgDelayAfterPwrEn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x010E - SG dGPU Reset Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100</span><br><span style="color: hsl(120, 100%, 40%);">+ microseconds</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SgDelayAfterHoldReset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0110 - MMIO size adjustment for AUTO mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Positive number means increasing MMIO size, Negative value means decreasing MMIO</span><br><span style="color: hsl(120, 100%, 40%);">+ size: 0 (Default)=no change to AUTO mode MMIO size</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MmioSizeAdjustment;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming</span><br><span style="color: hsl(120, 100%, 40%);">+ Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static</span><br><span style="color: hsl(120, 100%, 40%);">+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3ProgramStaticEq;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0113 - Enable/Disable PEG 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits</span><br><span style="color: hsl(120, 100%, 40%);">+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0114 - Enable/Disable PEG 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits</span><br><span style="color: hsl(120, 100%, 40%);">+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0115 - Enable/Disable PEG 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits</span><br><span style="color: hsl(120, 100%, 40%);">+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0116 - Enable/Disable PEG 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits</span><br><span style="color: hsl(120, 100%, 40%);">+ it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0117 - PEG 0 Max Link Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0MaxLinkSpeed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0118 - PEG 1 Max Link Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1MaxLinkSpeed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0119 - PEG 2 Max Link Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2MaxLinkSpeed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011A - PEG 3 Max Link Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3MaxLinkSpeed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011B - PEG 0 Max Link Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):</span><br><span style="color: hsl(120, 100%, 40%);">+ Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0MaxLinkWidth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011C - PEG 1 Max Link Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):</span><br><span style="color: hsl(120, 100%, 40%);">+ Limit Link to x2, (0x3):Limit Link to x4</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:x1, 2:x2, 3:x4</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1MaxLinkWidth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011D - PEG 2 Max Link Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):</span><br><span style="color: hsl(120, 100%, 40%);">+ Limit Link to x2</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:x1, 2:x2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2MaxLinkWidth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011E - PEG 3 Max Link Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):</span><br><span style="color: hsl(120, 100%, 40%);">+ Limit Link to x2</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:x1, 2:x2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3MaxLinkWidth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011F - Power down unused lanes on PEG 0</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based</span><br><span style="color: hsl(120, 100%, 40%);">+ on the max possible link width</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No power saving, 1:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0PowerDownUnusedLanes;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0120 - Power down unused lanes on PEG 1</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based</span><br><span style="color: hsl(120, 100%, 40%);">+ on the max possible link width</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No power saving, 1:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1PowerDownUnusedLanes;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0121 - Power down unused lanes on PEG 2</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based</span><br><span style="color: hsl(120, 100%, 40%);">+ on the max possible link width</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No power saving, 1:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2PowerDownUnusedLanes;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0122 - Power down unused lanes on PEG 3</span><br><span style="color: hsl(120, 100%, 40%);">+ (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based</span><br><span style="color: hsl(120, 100%, 40%);">+ on the max possible link width</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No power saving, 1:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3PowerDownUnusedLanes;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom</span><br><span style="color: hsl(120, 100%, 40%);">+ Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after</span><br><span style="color: hsl(120, 100%, 40%);">+ Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Before, 1:After</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 InitPcieAspmAfterOprom;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable SSC(0X1) - Disable SSC per platform design or for compliance testing</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Normal Operation, 1:Disable SSC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegDisableSpreadSpectrumClocking;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace4[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0128 - DMI Gen3 Root port preset values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3RootPortPreset[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0130 - DMI Gen3 End port preset values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3EndPointPreset[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0138 - DMI Gen3 End port Hint values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3EndPointHint[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3RxCtlePeaking[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction</span><br><span style="color: hsl(120, 100%, 40%);">+ caused by high package temperatures for processors that implement the Intel Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ Velocity Boost (TVB) feature</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbRatioClipping;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0145 - Thermal Velocity Boost voltage optimization</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations</span><br><span style="color: hsl(120, 100%, 40%);">+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbVoltageOptimization;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0146</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace5[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-15, 12 is default for each bundle, must be specified based upon platform design</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3RxCtlePeaking[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0152 - Memory data pointer for saved preset search results</span><br><span style="color: hsl(120, 100%, 40%);">+ The reference code will store the Gen3 Preset Search results in the SaDataHob's</span><br><span style="color: hsl(120, 100%, 40%);">+ PegData structure (SA_PEG_DATA) and platform code can save/restore this data to</span><br><span style="color: hsl(120, 100%, 40%);">+ skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PegDataPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0156 - PEG PERST# GPIO information</span><br><span style="color: hsl(120, 100%, 40%);">+ The reference code will use the information in this structure in order to reset</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Gen3 devices during equalization, if necessary</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGpioData[28];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Disable, 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegRootPortHPE[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0176 - DeEmphasis control for DMI</span><br><span style="color: hsl(120, 100%, 40%);">+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: -6dB, 1: -3.5dB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiDeEmphasis;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0177 - Selection of the primary display device</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PrimaryDisplay;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0178 - Selection of iGFX GTT Memory size</span><br><span style="color: hsl(120, 100%, 40%);">+ 1=2MB, 2=4MB, 3=8MB, Default is 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 1:2MB, 2:4MB, 3:8MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GttSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017A - Temporary MMIO address for GMADR</span><br><span style="color: hsl(120, 100%, 40%);">+ The reference code will use this as Temporary MMIO address space to access GMADR</span><br><span style="color: hsl(120, 100%, 40%);">+ Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to</span><br><span style="color: hsl(120, 100%, 40%);">+ (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress</span><br><span style="color: hsl(120, 100%, 40%);">+ - 0x1) (Where ApertureSize = 256MB)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GmAdr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017E - Temporary MMIO address for GTTMMADR</span><br><span style="color: hsl(120, 100%, 40%);">+ The reference code will use this as Temporary MMIO address space to access GTTMMADR</span><br><span style="color: hsl(120, 100%, 40%);">+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr</span><br><span style="color: hsl(120, 100%, 40%);">+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO</span><br><span style="color: hsl(120, 100%, 40%);">+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GttMmAdr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0182 - Selection of PSMI Region size</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsmiRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaRtd3Pcie0Gpio[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaRtd3Pcie1Gpio[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaRtd3Pcie2Gpio[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaRtd3Pcie3Gpio[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E3 - Enable/Disable MRC TXT dependency</span><br><span style="color: hsl(120, 100%, 40%);">+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TxtImplemented;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E4 - Enable/Disable SA OcSupport</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaOcSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E5 - GT slice Voltage Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Adaptive, 1: Override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Adaptive, 1: Override</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtVoltageMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E6 - Maximum GTs turbo ratio override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal/Auto, 60=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtMaxOcRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E7 - The voltage offset applied to GT slice</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 1000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 2000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtVoltageOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01EB - adaptive voltage applied during turbo frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 2000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtExtraTurboVoltage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01ED - voltage offset applied to the SA</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 1000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SaVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU</span><br><span style="color: hsl(120, 100%, 40%);">+ Root port Index number to indicate which PCIe root port has dGPU</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RootPortIndex;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F0 - Realtime Memory Timing</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform</span><br><span style="color: hsl(120, 100%, 40%);">+ realtime memory timing changes after MRC_DONE.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RealtimeMemoryTiming;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F1 - Enable/Disable SA IPU</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaIpuEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F2 - IPU IMR Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:IPU Camera, 1:IPU Gen Default is 0</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:IPU Camera, 1:IPU Gen</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaIpuImrConfiguration;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F3 - Selection of PSMI Support On/Off</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtPsmiSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F4 - GT unslice Voltage Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Adaptive, 1: Override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Adaptive, 1: Override</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtusVoltageMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F5 - voltage offset applied to GT unslice</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 2000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtusVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 2000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtusVoltageOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 2000=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 GtusExtraTurboVoltage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FB - Maximum GTus turbo ratio override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Minimal, 60=Maximum</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtusMaxOcRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FC - SaPreMemProductionRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Pre-Mem Production</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPreMemProductionRsvd[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0200 - BIST on Reset</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BistOnReset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipStopPbet;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0202 - C6DRAM power gating feature</span><br><span style="color: hsl(120, 100%, 40%);">+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM</span><br><span style="color: hsl(120, 100%, 40%);">+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating</span><br><span style="color: hsl(120, 100%, 40%);">+ feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableC6Dram;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0203 - Over clocking support</span><br><span style="color: hsl(120, 100%, 40%);">+ Over clocking support; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 OcSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0204 - Over clocking Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 OcLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0205 - Maximum Core Turbo Ratio Override</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CoreMaxOcRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0206 - Core voltage mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Core voltage mode; <b>0: Adaptive</b>; 1: Override.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CoreVoltageMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0207</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0208 - Maximum clr turbo ratio override</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RingMaxOcRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0209 - Hyper Threading Enable/Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HyperThreading;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020A - CPU ratio value</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020B - Boot frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo</span><br><span style="color: hsl(120, 100%, 40%);">+ is selected BIOS will start in max non-turbo mode and switch to Turbo mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0, 1:1, 2:2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BootFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020C - Number of active cores</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:</span><br><span style="color: hsl(120, 100%, 40%);">+ 2 </b>;<b>3: 3 </b></span><br><span style="color: hsl(120, 100%, 40%);">+ 0:All, 1:1, 2:2, 3:3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ActiveCoreCount;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020D - Processor Early Power On Configuration FCLK setting</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-</span><br><span style="color: hsl(120, 100%, 40%);">+ 2: 400 MHz. - 3: Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FClkFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020E - Set JTAG power in C10 and deeper power states</span><br><span style="color: hsl(120, 100%, 40%);">+ False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10</span><br><span style="color: hsl(120, 100%, 40%);">+ and deeper power states for debug purpose. <b>0: False</b>; 1: True.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: False, 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 JtagC10PowerGateDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020F - Enable or Disable VMX</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0210 - AVX2 Ratio Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Avx2RatioOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0211 - AVX3 Ratio Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Avx3RatioOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0212 - BCLK Adaptive Voltage Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable;<b> 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BclkAdaptiveVoltage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0213 - Core PLL voltage offset</span><br><span style="color: hsl(120, 100%, 40%);">+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CorePllVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0214 - core voltage override</span><br><span style="color: hsl(120, 100%, 40%);">+ The core voltage override which is applied to the entire range of cpu core frequencies.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 2000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CoreVoltageOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0216 - Core Turbo voltage Adaptive</span><br><span style="color: hsl(120, 100%, 40%);">+ Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 2000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CoreVoltageAdaptive;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0218 - Core Turbo voltage Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CoreVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021A - Ring Downbin</span><br><span style="color: hsl(120, 100%, 40%);">+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always</span><br><span style="color: hsl(120, 100%, 40%);">+ lower than the core ratio.0: Disable; <b>1: Enable.</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RingDownBin;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021B - Ring voltage mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Ring voltage mode; <b>0: Adaptive</b>; 1: Override.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RingVoltageMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021C - Ring voltage override</span><br><span style="color: hsl(120, 100%, 40%);">+ The ring voltage override which is applied to the entire range of cpu ring frequencies.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 2000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RingVoltageOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021E - Ring Turbo voltage Adaptive</span><br><span style="color: hsl(120, 100%, 40%);">+ Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 2000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RingVoltageAdaptive;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0220 - Ring Turbo voltage Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RingVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0222 - TjMax Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support</span><br><span style="color: hsl(120, 100%, 40%);">+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TjMaxOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0223 - BiosGuard</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BiosGuard;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0224</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BiosGuardToolsInterface;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0225 - EnableSgx</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable, 1: Enable, 2: Software Control</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableSgx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0226 - Txt</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Txt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0227</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0228 - PrmrrSize</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022C - SinitMemorySize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 SinitMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0230 - TxtHeapMemorySize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TxtHeapMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0234 - TxtDprMemorySize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TxtDprMemorySize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0238 - TxtDprMemoryBase</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 TxtDprMemoryBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0240 - BiosAcmBase</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BiosAcmBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0244 - BiosAcmSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BiosAcmSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0248 - ApStartupBase</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 ApStartupBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x024C - TgaSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TgaSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0250 - TxtLcpPdBase</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 TxtLcpPdBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0258 - TxtLcpPdSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 TxtLcpPdSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0260 - IsTPMPresence</span><br><span style="color: hsl(120, 100%, 40%);">+ IsTPMPresence default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IsTPMPresence;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0261 - ReservedSecurityPreMem</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for Security Pre-Mem</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedSecurityPreMem[15];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable PCH PCIe Gen 3 Set CTLE Value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioRxSetCtleEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 3 Set CTLE Value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioRxSetCtle[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen1DownscaleAmp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DownscaleAmp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen3DownscaleAmp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen1DeEmphEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen1DeEmph[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DeEmph3p5[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPcieHsioTxGen2DeEmph6p0[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen1EqBoostMag[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen2EqBoostMag[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioRxGen3EqBoostMag[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen1DownscaleAmp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen2DownscaleAmp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen3DownscaleAmp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen1DeEmphEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen1DeEmph[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen2DeEmphEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen2DeEmph[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen3DeEmphEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSataHsioTxGen3DeEmph[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding</span><br><span style="color: hsl(120, 100%, 40%);">+ Original LPC only decodes one byte of port 80h.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLpcEnhancePort8xhDecoding;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0451 - PCH Port80 Route</span><br><span style="color: hsl(120, 100%, 40%);">+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPort80Route;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0452 - Enable SMBus ARP support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SMBus ARP support.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SmbusArpEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0453 - Number of RsvdSmbusAddressTable.</span><br><span style="color: hsl(120, 100%, 40%);">+ The number of elements in the RsvdSmbusAddressTable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchNumRsvdSmbusAddresses;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0454 - SMBUS Base Address</span><br><span style="color: hsl(120, 100%, 40%);">+ SMBUS Base Address (IO space).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchSmbusIoBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0456 - Size of PCIe IMR.</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of PCIe IMR in megabytes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieImrSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0458 - Point of RsvdSmbusAddressTable</span><br><span style="color: hsl(120, 100%, 40%);">+ Array of addresses reserved for non-ARP-capable SMBus devices.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RsvdSmbusAddressTablePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x045C - Enable PCIE RP Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0</span><br><span style="color: hsl(120, 100%, 40%);">+ for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpEnableMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0460 - Enable PCIe IMR</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieImrEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0461 - Root port number for IMR.</span><br><span style="color: hsl(120, 100%, 40%);">+ Root port number for IMR.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ImrRpSelection;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0462 - Enable SMBus Alert Pin</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SMBus Alert Pin.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSmbAlertEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0463 - ReservedPchPreMem</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for Pch Pre-Mem</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedPchPreMem[13];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0470 - Debug Interfaces</span><br><span style="color: hsl(120, 100%, 40%);">+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,</span><br><span style="color: hsl(120, 100%, 40%);">+ BIT2 - Not used.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdDebugInterfaceFlags;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0471 - PcdSerialIoUartNumber</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart Controller for debug.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUartNumber;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0472 - ISA Serial Base selection</span><br><span style="color: hsl(120, 100%, 40%);">+ Select ISA Serial Base address. Default is 0x3F8.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:0x3F8, 1:0x2F8</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdIsaSerialUartBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0473 - GT PLL voltage offset</span><br><span style="color: hsl(120, 100%, 40%);">+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtPllVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0474 - Ring PLL voltage offset</span><br><span style="color: hsl(120, 100%, 40%);">+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RingPllVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0475 - System Agent PLL voltage offset</span><br><span style="color: hsl(120, 100%, 40%);">+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPllVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0476 - Memory Controller PLL voltage offset</span><br><span style="color: hsl(120, 100%, 40%);">+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McPllVoltageOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0477 - MRC Safe Config</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable MRC Safe Config</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MrcSafeConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0478 - PcdSerialDebugBaudRate</span><br><span style="color: hsl(120, 100%, 40%);">+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.</span><br><span style="color: hsl(120, 100%, 40%);">+ 3:9600, 4:19200, 6:56700, 7:115200</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialDebugBaudRate;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0479 - HobBufferSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB</span><br><span style="color: hsl(120, 100%, 40%);">+ total HOB size).</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HobBufferSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047A - Early Command Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Early Command Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ECT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047B - SenseAmp Offset Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable SenseAmp Offset Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SOT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047C - Early ReadMPR Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Early ReadMPR Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ERDMPRTC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047D - Read MPR Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read MPR Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDMPRT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047E - Receive Enable Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Receive Enable Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RCVET;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x047F - Jedec Write Leveling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Jedec Write Leveling</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 JWRL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0480 - Early Write Time Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Early Write Time Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EWRTC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0481 - Early Read Time Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Early Read Time Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ERDTC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0482 - Write Timing Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Timing Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRTC1D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0483 - Write Voltage Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Voltage Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRVC1D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0484 - Read Timing Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read Timing Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDTC1D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0485 - Dimm ODT Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Dimm ODT Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DIMMODTT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0486 - DIMM RON Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable DIMM RON Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DIMMRONT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0487 - Write Drive Strength/Equalization 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Drive Strength/Equalization 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRDSEQT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0488 - Write Slew Rate Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Slew Rate Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRSRT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0489 - Read ODT Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read ODT Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDODTT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048A - Read Equalization Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read Equalization Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDEQT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048B - Read Amplifier Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read Amplifier Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDAPT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048C - Write Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRTC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048D - Read Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read Timing Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDTC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048E - Write Voltage Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Voltage Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRVC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x048F - Read Voltage Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Read Voltage Centering 2D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RDVC2D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0490 - Command Voltage Centering</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Command Voltage Centering</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CMDVC;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0491 - Late Command Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Late Command Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 LCT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0492 - Round Trip Latency Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Round Trip Latency Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RTL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0493 - Turn Around Timing Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Turn Around Timing Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TAT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0494 - Memory Test</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Memory Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MEMTST;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0495 - DIMM SPD Alias Test</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable DIMM SPD Alias Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ALIASCHK;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0496 - Receive Enable Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Receive Enable Centering 1D</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RCVENC1D;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0497 - Retrain Margin Check</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Retrain Margin Check</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RMC;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0498 - Write Drive Strength Up/Dn independently</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Write Drive Strength Up/Dn independently</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WRDSUDT;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0499 - ECC Support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable ECC Support</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EccSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049A - Memory Remap</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Memory Remap</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RemapEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049B - Rank Interleave support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at</span><br><span style="color: hsl(120, 100%, 40%);">+ the same time.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RankInterleave;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049C - Enhanced Interleave support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Enhanced Interleave support</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnhancedInterleave;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049D - Memory Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of</span><br><span style="color: hsl(120, 100%, 40%);">+ equal size. This option may change TOLUD and REMAP values as needed.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryTrace;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049E - Ch Hash Support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChHashEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049F - Extern Therm Status</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Extern Therm Status</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableExtts;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A0 - Closed Loop Therm Manage</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Closed Loop Therm Manage</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableCltm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A1 - Open Loop Therm Manage</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Open Loop Therm Manage</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableOltm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A2 - DDR PowerDown and idle counter</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable DDR PowerDown and idle counter</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnablePwrDn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnablePwrDnLpddr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Use user provided power weights, scale factor, and channel power</span><br><span style="color: hsl(120, 100%, 40%);">+ floor values</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UserPowerWeightsEn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A5 - RAPL PL Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable RAPL PL Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim2Lock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A6 - RAPL PL 2 enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable RAPL PL 2 enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim2Ena;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A7 - RAPL PL 1 enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable RAPL PL 1 enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim1Ena;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A8 - SelfRefresh Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable SelfRefresh Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SrefCfgEna;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThrtCkeMinDefeatLpddr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AA - Throttler CKEMin Defeature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Throttler CKEMin Defeature</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThrtCkeMinDefeat;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AB - Enable RH Prevention</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable RH Prevention</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RhPrevention;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AC - Exit On Failure (MRC)</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable Exit On Failure (MRC)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ExitOnFailure;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AD - LPDDR Thermal Sensor</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable LPDDR Thermal Sensor</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdrThermalSensor;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP</span><br><span style="color: hsl(120, 100%, 40%);">+ Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ddr4DdpSharedClock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP</span><br><span style="color: hsl(120, 100%, 40%);">+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ddr4DdpSharedZq;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B0 - Ch Hash Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to</span><br><span style="color: hsl(120, 100%, 40%);">+ BITS [19:6</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ChHashMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B2 - Base reference clock value</span><br><span style="color: hsl(120, 100%, 40%);">+ Base reference clock value, in Hertz(Default is 125Hz)</span><br><span style="color: hsl(120, 100%, 40%);">+ 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BClkFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B6 - Ch Hash Interleaved Bit</span><br><span style="color: hsl(120, 100%, 40%);">+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave</span><br><span style="color: hsl(120, 100%, 40%);">+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChHashInterleaveBit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B7 - Energy Scale Factor</span><br><span style="color: hsl(120, 100%, 40%);">+ Energy Scale Factor, Default is 4</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnergyScaleFact;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B8 - EPG DIMM Idd3N</span><br><span style="color: hsl(120, 100%, 40%);">+ Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on</span><br><span style="color: hsl(120, 100%, 40%);">+ a per DIMM basis. Default is 26</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Idd3n;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04BA - EPG DIMM Idd3P</span><br><span style="color: hsl(120, 100%, 40%);">+ Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated</span><br><span style="color: hsl(120, 100%, 40%);">+ on a per DIMM basis. Default is 11</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Idd3p;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04BC - CMD Slew Rate Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable CMD Slew Rate Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CMDSR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04BD - CMD Drive Strength and Tx Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable CMD Drive Strength and Tx Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CMDDSEQ;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04BE - CMD Normalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable CMD Normalization</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CMDNORM;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Early DQ Write Drive Strength and Equalization Training</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EWRDSEQ;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C0 - RH Activation Probability</span><br><span style="color: hsl(120, 100%, 40%);">+ RH Activation Probability, Probability value is 1/2^(inputvalue)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RhActProbability;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C1 - RAPL PL 2 WindowX</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim2WindX;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C2 - RAPL PL 2 WindowY</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim2WindY;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C3 - RAPL PL 1 WindowX</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim1WindX;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C4 - RAPL PL 1 WindowY</span><br><span style="color: hsl(120, 100%, 40%);">+ Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplLim1WindY;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C5 - RAPL PL 2 Power</span><br><span style="color: hsl(120, 100%, 40%);">+ range[0;2^14-1]= [2047.875;0]in W, (224= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RaplLim2Pwr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C7 - RAPL PL 1 Power</span><br><span style="color: hsl(120, 100%, 40%);">+ range[0;2^14-1]= [2047.875;0]in W, (224= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 RaplLim1Pwr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmThresholdCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CA - Warm Threshold Ch0 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmThresholdCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CB - Warm Threshold Ch1 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmThresholdCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CC - Warm Threshold Ch1 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmThresholdCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CD - Hot Threshold Ch0 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotThresholdCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CE - Hot Threshold Ch0 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotThresholdCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CF - Hot Threshold Ch1 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotThresholdCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotThresholdCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D1 - Warm Budget Ch0 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmBudgetCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D2 - Warm Budget Ch0 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmBudgetCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D3 - Warm Budget Ch1 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmBudgetCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D4 - Warm Budget Ch1 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WarmBudgetCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D5 - Hot Budget Ch0 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotBudgetCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D6 - Hot Budget Ch0 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotBudgetCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D7 - Hot Budget Ch1 Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotBudgetCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D8 - Hot Budget Ch1 Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HotBudgetCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04D9 - Idle Energy Ch0Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IdleEnergyCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DA - Idle Energy Ch0Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IdleEnergyCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DB - Idle Energy Ch1Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IdleEnergyCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DC - Idle Energy Ch1Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IdleEnergyCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DD - PowerDown Energy Ch0Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PdEnergyCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DE - PowerDown Energy Ch0Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PdEnergyCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04DF - PowerDown Energy Ch1Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PdEnergyCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E0 - PowerDown Energy Ch1Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PdEnergyCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E1 - Activate Energy Ch0Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Activate Energy Contribution, range[255;0],(172= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ActEnergyCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E2 - Activate Energy Ch0Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Activate Energy Contribution, range[255;0],(172= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ActEnergyCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E3 - Activate Energy Ch1Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Activate Energy Contribution, range[255;0],(172= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ActEnergyCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E4 - Activate Energy Ch1Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Activate Energy Contribution, range[255;0],(172= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ActEnergyCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E5 - Read Energy Ch0Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Read Energy Contribution, range[255;0],(212= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RdEnergyCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E6 - Read Energy Ch0Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Read Energy Contribution, range[255;0],(212= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RdEnergyCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E7 - Read Energy Ch1Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Read Energy Contribution, range[255;0],(212= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RdEnergyCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E8 - Read Energy Ch1Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Read Energy Contribution, range[255;0],(212= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RdEnergyCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E9 - Write Energy Ch0Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Write Energy Contribution, range[255;0],(221= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WrEnergyCh0Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04EA - Write Energy Ch0Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Write Energy Contribution, range[255;0],(221= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WrEnergyCh0Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04EB - Write Energy Ch1Dimm0</span><br><span style="color: hsl(120, 100%, 40%);">+ Write Energy Contribution, range[255;0],(221= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WrEnergyCh1Dimm0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04EC - Write Energy Ch1Dimm1</span><br><span style="color: hsl(120, 100%, 40%);">+ Write Energy Contribution, range[255;0],(221= Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WrEnergyCh1Dimm1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04ED - Throttler CKEMin Timer</span><br><span style="color: hsl(120, 100%, 40%);">+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).</span><br><span style="color: hsl(120, 100%, 40%);">+ Dfault is 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThrtCkeMinTmr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04EE - Cke Rank Mapping</span><br><span style="color: hsl(120, 100%, 40%);">+ Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies</span><br><span style="color: hsl(120, 100%, 40%);">+ which rank CKE[i] goes to.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CkeRankMapping;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04EF - Rapl Power Floor Ch0</span><br><span style="color: hsl(120, 100%, 40%);">+ Power budget ,range[255;0],(0= 5.3W Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplPwrFlCh0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F0 - Rapl Power Floor Ch1</span><br><span style="color: hsl(120, 100%, 40%);">+ Power budget ,range[255;0],(0= 5.3W Def)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaplPwrFlCh1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F1 - Command Rate Support</span><br><span style="color: hsl(120, 100%, 40%);">+ CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnCmdRate;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F2 - REFRESH_2X_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Refresh2X;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F3 - Energy Performance Gain</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable(default) Energy Performance Gain.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EpgEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F4 - Row Hammer Solution</span><br><span style="color: hsl(120, 100%, 40%);">+ Type of method used to prevent Row Hammer. Default is Hardware RHP</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Hardware RHP, 1:2x Refresh</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RhSolution;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F5 - User Manual Threshold</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled: Predefined threshold will be used.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enabled: User Input will be used.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UserThresholdEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F6 - User Manual Budget</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled: Configuration of memories will defined the Budget value.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enabled: User Input will be used.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UserBudgetEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F7 - TcritMax</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax</span><br><span style="color: hsl(120, 100%, 40%);">+ has to be greater than THIGHMax .\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Critical temperature will be TcritMax </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodTcritMax;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F8 - Event mode </span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Comparator mode.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Interrupt mode</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodEventMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04F9 - EVENT polarity </span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Active LOW.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Active HIGH</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodEventPolarity;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FA - Critical event only</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Trips on alarm or critical.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Trips only if criticaal temperature is reached</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodCriticalEventOnly;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FB - Event output control</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Event output disable.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Event output enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodEventOutputControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FC - Alarm window lock bit</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Alarm trips are not locked and can be changed.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Alarm trips are locked and cannot be changed</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodAlarmwindowLockBit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FD - Critical trip lock bit</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Critical trip is not locked and can be changed.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Critical trip is locked and cannot be changed</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodCriticaltripLockBit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FE - Shutdown mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable:Temperature sensor enable.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable:Temperature sensor disable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodShutdownMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FF - ThighMax</span><br><span style="color: hsl(120, 100%, 40%);">+ Thigh = ThighMax (Default is 93)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodThigMax;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0500 - User Manual Thig and Tcrit</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(Default): Temperature will be given by the configuration of memories and</span><br><span style="color: hsl(120, 100%, 40%);">+ 1x or 2xrefresh rate.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enabled: User Input will define for Thigh and Tcrit.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TsodManualEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0501 - Force OLTM or 2X Refresh when needed</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(Default): = Force OLTM.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Enabled: = Force 2x Refresh.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ForceOltmOrRefresh2x;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0502 - Pwr Down Idle Timer</span><br><span style="color: hsl(120, 100%, 40%);">+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means</span><br><span style="color: hsl(120, 100%, 40%);">+ AUTO: 64 for ULX/ULT, 128 for DT/Halo</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PwdwnIdleCounter;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0503 - Bitmask of ranks that have CA bus terminated</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,</span><br><span style="color: hsl(120, 100%, 40%);">+ Rank0 is terminating and Rank1 is non-terminating</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CmdRanksTerminated;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0504 - GDXC MOT enable</span><br><span style="color: hsl(120, 100%, 40%);">+ GDXC MOT enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0505 - PcdSerialDebugLevel</span><br><span style="color: hsl(120, 100%, 40%);">+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,</span><br><span style="color: hsl(120, 100%, 40%);">+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,</span><br><span style="color: hsl(120, 100%, 40%);">+ Info & Verbose.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load</span><br><span style="color: hsl(120, 100%, 40%);">+ Error Warnings and Info, 5:Load Error Warnings Info and Verbose</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialDebugLevel;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0506 - Fivr Faults</span><br><span style="color: hsl(120, 100%, 40%);">+ Fivr Faults; 0: Disabled; <b>1: Enabled.</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FivrFaults;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0507 - Fivr Efficiency</span><br><span style="color: hsl(120, 100%, 40%);">+ Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FivrEfficiency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0508 - Safe Mode Support</span><br><span style="color: hsl(120, 100%, 40%);">+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SafeMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0509 - Ask MRC to clear memory content</span><br><span style="color: hsl(120, 100%, 40%);">+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CleanMemory;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050A - LpDdrDqDqsReTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables/Disable LpDdrDqDqsReTraining</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 LpDdrDqDqsReTraining;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050B - Post Code Output Port</span><br><span style="color: hsl(120, 100%, 40%);">+ This option configures Post Code Output Port</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PostCodeOutputPort;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050D - RMTLoopCount</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RMTLoopCount;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050E - BER Support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable the Rank Margin Tool interpolation/extrapolation.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnBER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050F - Dual Dimm Per-Channel Board Type</span><br><span style="color: hsl(120, 100%, 40%);">+ Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used</span><br><span style="color: hsl(120, 100%, 40%);">+ to limit maximum frequency for some SKUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:1DPC, 1:2DPC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DualDimmPerChannelBoardType;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0510</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[15];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_M_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M Test Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0520</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Signature;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0524 - Skip external display device scanning</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Do not scan for external display device, Disable (Default): Scan external</span><br><span style="color: hsl(120, 100%, 40%);">+ display devices</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipExtGfxScan;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0525 - Generate BIOS Data ACPI Table</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BdatEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM</span><br><span style="color: hsl(120, 100%, 40%);">+ Detect and report if external graphics device only support LegacyOpROM or not (to</span><br><span style="color: hsl(120, 100%, 40%);">+ support CSM auto-enable). Enable(Default)=1, Disable=0</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScanExtGfxForLegacyOpRom;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0527 - Lock PCU Thermal Management registers</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 LockPTMregs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0528 - DMI Max Link Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1</span><br><span style="color: hsl(120, 100%, 40%);">+ Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiMaxLinkSpeed;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0529 - DMI Equalization Phase 2</span><br><span style="color: hsl(120, 100%, 40%);">+ DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ AUTO - Use the current default method</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable phase2, 1:Enable phase2, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3EqPh2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052A - DMI Gen3 Equalization Phase3</span><br><span style="color: hsl(120, 100%, 40%);">+ DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,</span><br><span style="color: hsl(120, 100%, 40%);">+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software</span><br><span style="color: hsl(120, 100%, 40%);">+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static</span><br><span style="color: hsl(120, 100%, 40%);">+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase1), Disabled(0x4): Bypass Equalization Phase 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiGen3EqPh3Method;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable phase 2, Auto(0x2)(Default): Use the current default method</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0Gen3EqPh2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable phase 2, Auto(0x2)(Default): Use the current default method</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1Gen3EqPh2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable phase 2, Auto(0x2)(Default): Use the current default method</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2Gen3EqPh2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable phase 2, Auto(0x2)(Default): Use the current default method</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3Gen3EqPh2Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.</span><br><span style="color: hsl(120, 100%, 40%);">+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,</span><br><span style="color: hsl(120, 100%, 40%);">+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software</span><br><span style="color: hsl(120, 100%, 40%);">+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static</span><br><span style="color: hsl(120, 100%, 40%);">+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase1), Disabled(0x4): Bypass Equalization Phase 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg0Gen3EqPh3Method;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.</span><br><span style="color: hsl(120, 100%, 40%);">+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,</span><br><span style="color: hsl(120, 100%, 40%);">+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software</span><br><span style="color: hsl(120, 100%, 40%);">+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static</span><br><span style="color: hsl(120, 100%, 40%);">+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase1), Disabled(0x4): Bypass Equalization Phase 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg1Gen3EqPh3Method;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.</span><br><span style="color: hsl(120, 100%, 40%);">+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,</span><br><span style="color: hsl(120, 100%, 40%);">+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software</span><br><span style="color: hsl(120, 100%, 40%);">+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static</span><br><span style="color: hsl(120, 100%, 40%);">+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase1), Disabled(0x4): Bypass Equalization Phase 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg2Gen3EqPh3Method;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.</span><br><span style="color: hsl(120, 100%, 40%);">+ PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,</span><br><span style="color: hsl(120, 100%, 40%);">+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software</span><br><span style="color: hsl(120, 100%, 40%);">+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static</span><br><span style="color: hsl(120, 100%, 40%);">+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just</span><br><span style="color: hsl(120, 100%, 40%);">+ Phase1), Disabled(0x4): Bypass Equalization Phase 3</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Peg3Gen3EqPh3Method;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming</span><br><span style="color: hsl(120, 100%, 40%);">+ Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static</span><br><span style="color: hsl(120, 100%, 40%);">+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3ProgramStaticEq;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt</span><br><span style="color: hsl(120, 100%, 40%);">+ Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test</span><br><span style="color: hsl(120, 100%, 40%);">+ and generate new EQ values every boot, not recommended</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Gen3SwEqAlwaysAttempt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq</span><br><span style="color: hsl(120, 100%, 40%);">+ Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test</span><br><span style="color: hsl(120, 100%, 40%);">+ Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the</span><br><span style="color: hsl(120, 100%, 40%);">+ current default method (Default)Auto will test Presets 7, 3, and 5. It is possible</span><br><span style="color: hsl(120, 100%, 40%);">+ for this default to change over time;using Auto will ensure Reference Code always</span><br><span style="color: hsl(120, 100%, 40%);">+ uses the latest default settings</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:P7 P3 P5, 1:P0 to P9, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Gen3SwEqNumberOfPresets;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ Use the current default</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Gen3SwEqEnableVocTest;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0537 - PCIe Rx Compliance Testing Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;</span><br><span style="color: hsl(120, 100%, 40%);">+ it should only be set when doing PCIe compliance testing</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegRxCemTestingMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegRxCemLoopbackLane;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0539 - Generate PCIe BDAT Margin Table</span><br><span style="color: hsl(120, 100%, 40%);">+ Set this policy to enable the generation and addition of PCIe margin data to the</span><br><span style="color: hsl(120, 100%, 40%);">+ BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin</span><br><span style="color: hsl(120, 100%, 40%);">+ data generation, Enable(0x1): Generate PCIe BDAT margin data</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGenerateBdatMarginTable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing</span><br><span style="color: hsl(120, 100%, 40%);">+ Set this policy to enable the generation and addition of PCIe margin data to the</span><br><span style="color: hsl(120, 100%, 40%);">+ BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for</span><br><span style="color: hsl(120, 100%, 40%);">+ compliance testing</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegRxCemNonProtocolAwareness;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x053B - PCIe Override RxCTLE</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE</span><br><span style="color: hsl(120, 100%, 40%);">+ peak values unmodified</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3RxCtleOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x053C - Rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE</span><br><span style="color: hsl(120, 100%, 40%);">+ peak values unmodified</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3Rsvd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x053D - PEG Gen3 Root port preset values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3RootPortPreset[20];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0551 - PEG Gen3 End port preset values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3EndPointPreset[20];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0565 - PEG Gen3 End port Hint values per lane</span><br><span style="color: hsl(120, 100%, 40%);">+ Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegGen3EndPointHint[20];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0579</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-65535, default is 1000. @warning Do not change from the default</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Gen3SwEqJitterDwellTime;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-65535, default is 1. @warning Do not change from the default</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Gen3SwEqJitterErrorTarget;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-65535, default is 10000. @warning Do not change from the default</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Gen3SwEqVocDwellTime;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0-65535, default is 2. @warning Do not change from the default</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Gen3SwEqVocErrorTarget;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0582 - Panel Power Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Control for enabling/disabling VDD force bit (Required only for early enabling of</span><br><span style="color: hsl(120, 100%, 40%);">+ eDP panel). 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PanelPowerEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0583 - BdatTestType</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Rank Margin Tool, 1:Margin2D</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BdatTestType;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0584 - SaPreMemTestRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Pre-Mem Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPreMemTestRsvd[12];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0590 - TotalFlashSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 TotalFlashSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0592 - BiosSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BiosSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0594 - TxtAcheckRequest</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TxtAcheckRequest;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0595 - SecurityTestRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Pre-Mem Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SecurityTestRsvd[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0598 - Smbus dynamic power gating</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable or Enable Smbus dynamic power gating.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SmbusDynamicPowerGating;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0599 - Disable and Lock Watch Dog Register</span><br><span style="color: hsl(120, 100%, 40%);">+ Set 1 to clear WDT status, then disable and lock WDT registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WdtDisableAndLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059A - SMBUS SPD Write Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable bit. For security recommendations, SPD write disable bit must be set.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SmbusSpdWriteDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059B - ChipsetInit HECI message</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.</span><br><span style="color: hsl(120, 100%, 40%);">+ If disabled, it prevents from sending ChipsetInit HECI message. </span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChipsetInitMessage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059C - Bypass ChipsetInit sync reset.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BypassPhySyncReset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059D - Force ME DID Init Status</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set</span><br><span style="color: hsl(120, 100%, 40%);">+ ME DID init stat value</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DidInitStat;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059E - CPU Replaced Polling Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableCpuReplacedPolling;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x059F - ME DID Message</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent</span><br><span style="color: hsl(120, 100%, 40%);">+ the DID message from being sent)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SendDidMsg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A0 - Retry mechanism for HECI APIs</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Enable/Disable HECI retry.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableHeciRetry;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A1 - Check HECI message before send</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Enable/Disable message check.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableMessageCheck;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A2 - Skip MBP HOB</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Enable/Disable MOB HOB.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipMbpHob;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A3 - HECI2 Interface Communication</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HeciCommunication2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A4 - Enable KT device</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Enable or Disable KT device.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 KtDeviceEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A5 - tRd2RdSG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2RdSG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A6 - tRd2RdDG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Read commands in different Bank Group for DDR4. All other</span><br><span style="color: hsl(120, 100%, 40%);">+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2RdDG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A7 - tRd2RdDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2RdDR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A8 - tRd2RdDD</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2RdDD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05A9 - tWr2RdSG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2RdSG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AA - tWr2RdDG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Read commands in different Bank Group for DDR4. All other</span><br><span style="color: hsl(120, 100%, 40%);">+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2RdDG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AB - tWr2RdDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2RdDR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AC - tWr2RdDD</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2RdDD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AD - tWr2WrSG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2WrSG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AE - tWr2WrDG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Write commands in different Bank Group for DDR4. All other</span><br><span style="color: hsl(120, 100%, 40%);">+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2WrDG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05AF - tWr2WrDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2WrDR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B0 - tWr2WrDD</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWr2WrDD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B1 - tRd2WrSG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2WrSG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B2 - tRd2WrDG</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Write commands in different Bank Group for DDR4. All other</span><br><span style="color: hsl(120, 100%, 40%);">+ DDR technologies should set this equal to SG. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2WrDG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B3 - tRd2WrDR</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2WrDR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B4 - tRd2WrDD</span><br><span style="color: hsl(120, 100%, 40%);">+ Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRd2WrDD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B5 - tRRD_L</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRRD_L;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B6 - tRRD_S</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ AUTO, max: 31</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tRRD_S;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B7 - tWTR_L</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:</span><br><span style="color: hsl(120, 100%, 40%);">+ AUTO, max: 60</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWTR_L;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B8 - tWTR_S</span><br><span style="color: hsl(120, 100%, 40%);">+ Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: AUTO, max: 28</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 tWTR_S;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05B9</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmTestUpd[3];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_M_TEST_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp M UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSPM_ARCH_UPD FspmArchUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_CONFIG FspmConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x051F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0520</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_M_TEST_CONFIG FspmTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05BC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPM_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..5725dd3</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>@@ -0,0 +1,3243 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPSUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPSUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Azalia Header structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 VendorId; ///< Codec Vendor ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< Codec Device ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
</span><br><span style="color: hsl(120, 100%, 40%);">+} AZALIA_HEADER;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Audio Azalia Verb Table structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_HEADER Header; ///< AZALIA PCH header
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
</span><br><span style="color: hsl(120, 100%, 40%);">+} AUDIO_AZALIA_VERB_TABLE;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Refer to the definition of PCH_INT_PIN
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchNoInt, ///< No Interrupt Pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntA,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntB,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntC,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntD
</span><br><span style="color: hsl(120, 100%, 40%);">+} SI_PCH_INT_PIN;
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Device; ///< Device number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Function; ///< Device function
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Irq; ///< IRQ to be set for device.
</span><br><span style="color: hsl(120, 100%, 40%);">+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020 - Logo Pointer</span><br><span style="color: hsl(120, 100%, 40%);">+ Points to PEI Display Logo Image</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 LogoPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0024 - Logo Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of PEI Display Logo Image</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 LogoSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0028 - Graphics Configuration Ptr</span><br><span style="color: hsl(120, 100%, 40%);">+ Points to VBT</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GraphicsConfigPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002C - Enable Device 4</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Device 4</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Device4Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002D - Enable HD Audio DSP</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DSP feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaDspEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002E</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0031 - Enable eMMC Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable eMMC Controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsEmmcEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0032 - Enable eMMC HS400 Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable eMMC HS400 Mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsEmmcHs400Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0033 - Enable SdCard Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SD Card Controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsSdCardEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0034 - Show SPI controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable to show SPI controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ShowSpiController;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0035</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0038 - MicrocodeRegionBase</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Base of Microcode Updates</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x003C - MicrocodeRegionSize</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of Microcode Updates</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040 - Turbo Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Turbo mode. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TurboMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0041 - Enable SATA SALP Support</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA Aggressive Link Power Management.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataSalpSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0042 - Enable SATA ports</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,</span><br><span style="color: hsl(120, 100%, 40%);">+ and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsEnable[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x004A - Enable SATA DEVSLP Feature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each</span><br><span style="color: hsl(120, 100%, 40%);">+ port, byte0 for port0, byte1 for port1, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsDevSlp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0052 - Enable USB2 ports</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for</span><br><span style="color: hsl(120, 100%, 40%);">+ port1, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PortUsb20Enable[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0062 - Enable USB3 ports</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for</span><br><span style="color: hsl(120, 100%, 40%);">+ port1, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PortUsb30Enable[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006C - Enable xDCI controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable to xDCI controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 XdciEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006D</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace2[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x006F - Enable SerialIo Device Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable</span><br><span style="color: hsl(120, 100%, 40%);">+ SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device</span><br><span style="color: hsl(120, 100%, 40%);">+ mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,</span><br><span style="color: hsl(120, 100%, 40%);">+ and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoDevMode[12];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.</span><br><span style="color: hsl(120, 100%, 40%);">+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DevIntConfigPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x007F - Number of DevIntConfig Entry</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr</span><br><span style="color: hsl(120, 100%, 40%);">+ must not be NULL.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 NumOfDevIntConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0080 - PIRQx to IRQx Map Config</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for</span><br><span style="color: hsl(120, 100%, 40%);">+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy</span><br><span style="color: hsl(120, 100%, 40%);">+ 8259 PCI mode.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PxRcConfig[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0088 - Select GPIO IRQ Route</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO IRQ Select. The valid value is 14 or 15.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GpioIrqRoute;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0089 - Select SciIrqSelect</span><br><span style="color: hsl(120, 100%, 40%);">+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SciIrqSelect;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008A - Select TcoIrqSelect</span><br><span style="color: hsl(120, 100%, 40%);">+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TcoIrqSelect;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008B - Enable/Disable Tco IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable TCO IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TcoIrqEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008C - PCH HDA Verb Table Entry Number</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of Entries in Verb Table.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaVerbTableEntryNum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x008D - PCH HDA Verb Table Pointer</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer to Array of pointers to Verb Table.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PchHdaVerbTablePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability</span><br><span style="color: hsl(120, 100%, 40%);">+ Capability to detect wake initiated by a codec in Sx</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaCodecSxWakeCapability;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0092 - Enable SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable SATA controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0093 - SATA Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SATA controller working mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:AHCI, 1:RAID</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0094 - USB Per Port HS Preemphasis Bias</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePetxiset[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A4 - USB Per Port HS Transmitter Bias</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfeTxiset[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,</span><br><span style="color: hsl(120, 100%, 40%);">+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePredeemp[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.</span><br><span style="color: hsl(120, 100%, 40%);">+ One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePehalfbit[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value</span><br><span style="color: hsl(120, 100%, 40%);">+ in arrary can be between 0-1. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDeEmphEnable[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDeEmph[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value</span><br><span style="color: hsl(120, 100%, 40%);">+ in arrary can be between 0-1. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment</span><br><span style="color: hsl(120, 100%, 40%);">+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default</span><br><span style="color: hsl(120, 100%, 40%);">+ = 00h</b>. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3HsioTxDownscaleAmp[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FC - Enable LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable LAN controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLanEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FD - Enable HD Audio Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkHda;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FE - Enable HD Audio DMIC0 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkDmic0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00FF - Enable HD Audio DMIC1 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkDmic1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0100 - Enable HD Audio SSP0 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0101 - Enable HD Audio SSP1 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0102 - Enable HD Audio SSP2 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SSP2/I2S link.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSsp2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW1 link. Muxed with HDA.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW2 link. Muxed with SSP1.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaAudioLinkSndw4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaSndwBufferRcomp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0108 - PTM for PCIE RP Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ One bit for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpPtmMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x010C - DPC for PCIE RP Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ One bit for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpDpcMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0110 - DPC Extensions PCIE RP Mask</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit</span><br><span style="color: hsl(120, 100%, 40%);">+ for each port, bit0 for port1, bit1 for port2, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcieRpDpcExtensionsMask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0114 - USB PDO Programming</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming</span><br><span style="color: hsl(120, 100%, 40%);">+ during later phase. 1: enable, 0: disable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UsbPdoProgramming;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0115 - Power button debounce configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will</span><br><span style="color: hsl(120, 100%, 40%);">+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PmcPowerButtonDebounce;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH eSPI Master and Slave BME enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEspiBmeMasterSlaveEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011A - PCH SATA use RST Legacy OROM</span><br><span style="color: hsl(120, 100%, 40%);">+ Use PCH SATA RST Legacy OROM when CSM is Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstLegacyOrom;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011B - Trace Hub Memory Base</span><br><span style="color: hsl(120, 100%, 40%);">+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate</span><br><span style="color: hsl(120, 100%, 40%);">+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub</span><br><span style="color: hsl(120, 100%, 40%);">+ memory is configured properly.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TraceHubMemBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x011F - PMC Debug Message Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW</span><br><span style="color: hsl(120, 100%, 40%);">+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcDbgMsgEn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0120 - PchPostMemRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for PCH Post-Mem</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPostMemRsvd[37];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0145 - Enable Ufs Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/disable Ufs 2.0 Controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ScsUfsEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0146 - CNVi Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]</span><br><span style="color: hsl(120, 100%, 40%);">+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCnviMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0147 - SdCard power enable polarity</span><br><span style="color: hsl(120, 100%, 40%);">+ Choose SD_PWREN# polarity</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Active low, 1: Active high</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SdCardPowerEnableActiveHigh;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0148 - PCH USB2 PHY Power Gating enable</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY</span><br><span style="color: hsl(120, 100%, 40%);">+ Sus Well PG</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsb2PhySusPgEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0149 - PCH USB OverCurrent mapping enable</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin</span><br><span style="color: hsl(120, 100%, 40%);">+ mapping allow for NOA usage of OC pins</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUsbOverCurrentEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014A</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014B - CNVi MfUart1 Type</span><br><span style="color: hsl(120, 100%, 40%);">+ This option configures Uart type which connects to MfUart1</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCnviMfUart1Type;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014C - Espi Lgmr Memory Range decode </span><br><span style="color: hsl(120, 100%, 40%);">+ This option enables or disables espi lgmr </span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEspiLgmrEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014D - HECI3 state</span><br><span style="color: hsl(120, 100%, 40%);">+ The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Heci3Enabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014E</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x014F - PCHHOT# pin</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHotEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0150 - SATA LED</span><br><span style="color: hsl(120, 100%, 40%);">+ SATA LED indicating SATA controller activity. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataLedEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0151 - VRAlert# Pin</span><br><span style="color: hsl(120, 100%, 40%);">+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmVrAlert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0152 - SLP_S0 VM Dynamic Control</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0VmRuntimeControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0153 - SLP_S0 VM 0.70V Support</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Vm070VSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0154 - SLP_S0 VM 0.75V Support</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Vm075VSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0155 - AMT Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0156 - WatchDog Timer Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 WatchDog;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0157 - ASF Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AsfEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0158 - Manageability Mode set by Mebx</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ManageabilityMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0159 - PET Progress</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive</span><br><span style="color: hsl(120, 100%, 40%);">+ PET Events.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FwProgress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015A - SOL Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtSolEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015B - OS Timer</span><br><span style="color: hsl(120, 100%, 40%);">+ 16 bits Value, Set OS watchdog timer.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 WatchDogTimerOs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015D - BIOS Timer</span><br><span style="color: hsl(120, 100%, 40%);">+ 16 bits Value, Set BIOS watchdog timer.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 WatchDogTimerBios;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x015F - Remote Assistance Trigger Availablilty</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RemoteAssistance;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0160 - KVM Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AmtKvmEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0161 - KVM Switch</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ForcMebxSyncUp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0162</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace5[1];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0163 - PCH PCIe root port connection type</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: built-in device, 1:slot</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSlotImplemented[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017B - Usage type for ClkSrc</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use</span><br><span style="color: hsl(120, 100%, 40%);">+ (free running), 0xFF: not used</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieClkSrcUsage[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x018B - ClkReq-to-ClkSrc mapping</span><br><span style="color: hsl(120, 100%, 40%);">+ Number of ClkReq signal assigned to ClkSrc</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieClkSrcClkReq[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x019B - PCIE RP Access Control Services Extended Capability</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCIE RP Access Control Services Extended Capability</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAcsEnabled[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01B3 - PCIE RP Clock Power Management</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal</span><br><span style="color: hsl(120, 100%, 40%);">+ can still be controlled by L1 PM substates mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpEnableCpm[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01CB - PCIE RP Detect Timeout Ms</span><br><span style="color: hsl(120, 100%, 40%);">+ The number of milliseconds within 0~65535 in reference code will wait for link to</span><br><span style="color: hsl(120, 100%, 40%);">+ exit Detect state for enabled ports before assuming there is no device and potentially</span><br><span style="color: hsl(120, 100%, 40%);">+ disabling the port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpDetectTimeoutMs[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH-H. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcModPhySusPgEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FC - SlpS0WithGbeSupport</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0WithGbeSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x01FD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0200 - Enable/Disable SA CRID</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: SA CRID, Disable (Default): SA CRID</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CridEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0201 - DMI ASPM</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:L0s, 2:L1, 3:L0sL1</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiAspm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0202 - PCIe DeEmphasis control per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: -6dB, 1(Default): -3.5dB</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:-6dB, 1:-3.5dB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegDeEmphasis[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0206 - PCIe Slot Power Limit value per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ Slot power limit value per root port</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegSlotPowerLimitValue[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020A - PCIe Slot Power Limit scale per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ Slot power limit scale per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegSlotPowerLimitScale[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x020E - PCIe Physical Slot Number per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ Physical Slot Number per root port</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PegPhysicalSlotNumber[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0216 - Enable/Disable PavpEnable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PavpEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0217 - CdClock Frequency selection</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CdClock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PeiGraphicsPeimInit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0219</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021A - Enable or disable GNA device</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GnaEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable/Clear, 1=Enable/Set</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 X2ApicOptOut;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x021C - Base addresses for VT-d function MMIO access</span><br><span style="color: hsl(120, 100%, 40%);">+ Base addresses for VT-d MMIO access per VT-d engine</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VtdBaseAddress[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0228 - Enable or disable eDP device</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortEdp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0229 - Enable or disable HPD of DDI port B</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortBHpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022A - Enable or disable HPD of DDI port C</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortCHpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022B - Enable or disable HPD of DDI port D</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortDHpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022C - Enable or disable HPD of DDI port F</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortFHpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022D - Enable or disable DDC of DDI port B</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortBDdc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022E - Enable or disable DDC of DDI port C</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortCDdc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x022F - Enable or disable DDC of DDI port D</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable, 1(Default)=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortDDdc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0230 - Enable or disable DDC of DDI port F</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default)=Disable, 1=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DdiPortFDdc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full</span><br><span style="color: hsl(120, 100%, 40%);">+ CD clock in S3 resume due to GOP absent</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipS3CdClockInit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms</span><br><span style="color: hsl(120, 100%, 40%);">+ Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate</span><br><span style="color: hsl(120, 100%, 40%);">+ T12 Delay to max 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeltaT12PowerCycleDelay;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0234 - Blt Buffer Address</span><br><span style="color: hsl(120, 100%, 40%);">+ Address of Blt buffer</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BltBufferAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0238 - Blt Buffer Size</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BltBufferSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x023C - SaPostMemProductionRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Post-Mem Production</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPostMemProductionRsvd[35];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for</span><br><span style="color: hsl(120, 100%, 40%);">+ Alpine ridge </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRootPortGen2PllL1CgDisable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0277 - Advanced Encryption Standard (AES) feature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AesEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0278 - Power State 3 enable/disable</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Psi3Enable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x027D - Power State 4 enable/disable</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For</span><br><span style="color: hsl(120, 100%, 40%);">+ all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Psi4Enable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0282 - Imon slope correction</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ImonSlope[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0287 - Imon offset correction</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.</span><br><span style="color: hsl(120, 100%, 40%);">+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ImonOffset[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x028C - Enable/Disable BIOS configuration of VR</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VrConfigEnable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0291 - Thermal Design Current enable/disable</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable.For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcEnable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0296 - HECI3 state</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms</span><br><span style="color: hsl(120, 100%, 40%);">+ , 8 - 8ms , 10 - 10ms.For all VR Indexe</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcTimeWindow[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x029B - Thermal Design Current Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For</span><br><span style="color: hsl(120, 100%, 40%);">+ all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TdcLock[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A0 - Platform Psys slope correction</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in</span><br><span style="color: hsl(120, 100%, 40%);">+ 1/100 increment values. Range is 0-200. 125 = 1.25</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysSlope;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A1 - Platform Psys offset correction</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-255. Value of 100 = 100/4 = 25 offset</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A2 - Acoustic Noise Mitigation feature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AcousticNoiseMitigation;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableIa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForIa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForGt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForSa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02A7 - Thermal Design Current current limit</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 TdcPowerLimit[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02B1 - AcLoadline</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 AcLoadline[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02BB</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02C5 - DcLoadline</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DcLoadline[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02CF - Power State 1 Threshold current</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi1Threshold[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02D9 - Power State 2 Threshold current</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi2Threshold[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02E3 - Power State 3 Threshold current</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Psi3Threshold[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02ED - Icc Max limit</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 IccMax[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x02F7 - VR Voltage Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 VrVoltageLimit[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableGt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableSa;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0303 - Enable VR specific mailbox command</span><br><span style="color: hsl(120, 100%, 40%);">+ VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A</span><br><span style="color: hsl(120, 100%, 40%);">+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific</span><br><span style="color: hsl(120, 100%, 40%);">+ command sent for PS4 exit issue. 11b - Reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SendVrMbxCmd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0304 - Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0305 - Enable or Disable TXT</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TxtEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0306</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9[6];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030C - Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ When this is skipped, boot loader must initialize processors before SilicionInit</span><br><span style="color: hsl(120, 100%, 40%);">+ API. </b>0: Initialize; <b>1: Skip</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipMpInit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030D - McIVR RFI Frequency Prefix</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ Minus (-).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrRfiFrequencyPrefix;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030E - McIVR RFI Frequency Adjustment</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in</span><br><span style="color: hsl(120, 100%, 40%);">+ increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrRfiFrequencyAdjust;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x030F - FIVR RFI Frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:</span><br><span style="color: hsl(120, 100%, 40%);">+ Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;</span><br><span style="color: hsl(120, 100%, 40%);">+ 0-1535 (Up to 153.5MHz) for 19MHz clock.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 FivrRfiFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0311 - McIVR RFI Spread Spectrum</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-</span><br><span style="color: hsl(120, 100%, 40%);">+ 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 McivrSpreadSpectrum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0312 - FIVR RFI Spread Spectrum</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;</span><br><span style="color: hsl(120, 100%, 40%);">+ Range: 0.0% to 10.0% (0-100).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FivrSpreadSpectrum;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation</span><br><span style="color: hsl(120, 100%, 40%);">+ feature enabled. <b>0: False</b>; 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FastPkgCRampDisableFivr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain</span><br><span style="color: hsl(120, 100%, 40%);">+ Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic</span><br><span style="color: hsl(120, 100%, 40%);">+ Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlowSlewRateForFivr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0315 - CpuBistData</span><br><span style="color: hsl(120, 100%, 40%);">+ Pointer CPU BIST Data</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CpuBistData;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.</span><br><span style="color: hsl(120, 100%, 40%);">+ Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox</span><br><span style="color: hsl(120, 100%, 40%);">+ command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IslVrCmd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x031A - Imon slope1 correction</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.</span><br><span style="color: hsl(120, 100%, 40%);">+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ImonSlope1[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0324 - CPU VR Power Delivery Design</span><br><span style="color: hsl(120, 100%, 40%);">+ Used to communicate the power delivery design capability of the board. This value</span><br><span style="color: hsl(120, 100%, 40%);">+ is an enum of the available power delivery segments that are defined in the Platform</span><br><span style="color: hsl(120, 100%, 40%);">+ Design Guide.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VrPowerDeliveryDesign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0328 - ReservedCpuPostMemProduction</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for CPU Post-Mem Production</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemProduction[1];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0329</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace10[29];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0346 - Enable DMI ASPM</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiAspm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0347 - Enable Power Optimizer</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable DMI Power Optimizer on PCH side.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPwrOptEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble</span><br><span style="color: hsl(120, 100%, 40%);">+ Write or erase is blocked by hardware.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchWriteProtectionEnable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x034D - PCH Flash Protection Ranges Read Enble</span><br><span style="color: hsl(120, 100%, 40%);">+ Read is blocked by hardware.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchReadProtectionEnable[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0352 - PCH Protect Range Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for</span><br><span style="color: hsl(120, 100%, 40%);">+ limit comparison.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchProtectedRangeLimit[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x035C - PCH Protect Range Base</span><br><span style="color: hsl(120, 100%, 40%);">+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchProtectedRangeBase[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0366 - Enable Pme</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Azalia wake-on-ring.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaPme;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0367</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace11;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0368 - VC Type</span><br><span style="color: hsl(120, 100%, 40%);">+ Virtual Channel Type Select: 0: VC0, 1: VC1.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: VC0, 1: VC1</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaVcType;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0369 - HD Audio Link Frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 6MHz, 1: 12MHz, 2: 24MHz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaLinkFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036A - iDisp-Link Frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.</span><br><span style="color: hsl(120, 100%, 40%);">+ 4: 96MHz, 3: 48MHz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispLinkFrequency;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036B - iDisp-Link T-mode</span><br><span style="color: hsl(120, 100%, 40%);">+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 2T, 1: 1T</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispLinkTmode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox</span><br><span style="color: hsl(120, 100%, 40%);">+ driver or SST driver supported).</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaDspUaaCompliance;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036D - iDisplay Audio Codec disconnection</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchHdaIDispCodecDisconnect;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x036E</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace12[15];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037D - Enable PCH Io Apic Entry 24-119</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIoApicEntry24_119;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037E - PCH Io Apic ID</span><br><span style="color: hsl(120, 100%, 40%);">+ This member determines IOAPIC ID. Default is 0x02.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIoApicId;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x037F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace13;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshSpiGpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshUart0GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshUart1GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c0GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c1GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshI2c2GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp0GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp1GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp2GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp3GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp4GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp5GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp6GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshGp7GpioAssign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038E - PCH ISH PDT Unlock Msg</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: False; 1: True.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchIshPdtUnlock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLanLtrEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0390</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace14[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region</span><br><span style="color: hsl(120, 100%, 40%);">+ protection.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownBiosLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0394 - PCH Compatibility Revision ID</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether or not the CRID feature of PCH should be enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchCrid;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0395 - RTC CMOS MEMORY LOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper</span><br><span style="color: hsl(120, 100%, 40%);">+ and and lower 128-byte bank of RTC RAM.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownRtcMemoryLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0396 - Enable PCIE RP HotPlug</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the root port is hot plug available.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpHotPlug[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AE - Enable PCIE RP Pm Sci</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the root port power manager SCI is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPmSci[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03C6 - Enable PCIE RP Ext Sync</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the extended synch is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpExtSync[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Transmitter Half Swing is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpTransmitterHalfSwing[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect</span><br><span style="color: hsl(120, 100%, 40%);">+ Probe CLKREQ# signal before enabling CLKREQ# based power management.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpClkReqDetect[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x040E - PCIE RP Advanced Error Report</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Advanced Error Reporting is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAdvancedErrorReporting[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0426 - PCIE RP Unsupported Request Report</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Unsupported Request Report is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpUnsupportedRequestReport[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x043E - PCIE RP Fatal Error Report</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Fatal Error Report is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpFatalErrorReport[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0456 - PCIE RP No Fatal Error Report</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the No Fatal Error Report is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNoFatalErrorReport[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x046E - PCIE RP Correctable Error Report</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the Correctable Error Report is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpCorrectableErrorReport[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0486 - PCIE RP System Error On Fatal Error</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Fatal Error is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnFatalError[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x049E - PCIE RP System Error On Non Fatal Error</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Non Fatal Error is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnNonFatalError[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04B6 - PCIE RP System Error On Correctable Error</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicate whether the System Error on Correctable Error is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSystemErrorOnCorrectableError[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04CE - PCIE RP Max Payload</span><br><span style="color: hsl(120, 100%, 40%);">+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpMaxPayload[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04E6</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace15[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x04FE - PCIE RP Pcie Speed</span><br><span style="color: hsl(120, 100%, 40%);">+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_SPEED).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPcieSpeed[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: hardware equalization; 4: Fixed Coeficients.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpGen3EqPh3Method[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x052E - PCIE RP Physical Slot Number</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates the slot number for the root port. Default is the value as root port index.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpPhysicalSlotNumber[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0546 - PCIE RP Completion Timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpCompletionTimeout[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x055E</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace16[106];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05C8 - PCIE RP Aspm</span><br><span style="color: hsl(120, 100%, 40%);">+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is</span><br><span style="color: hsl(120, 100%, 40%);">+ PchPcieAspmAutoConfig.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpAspm[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05E0 - PCIE RP L1 Substates</span><br><span style="color: hsl(120, 100%, 40%);">+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).</span><br><span style="color: hsl(120, 100%, 40%);">+ Default is PchPcieL1SubstatesL1_1_2.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpL1Substates[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x05F8 - PCIE RP Ltr Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting Mechanism.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpLtrEnable[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0610 - PCIE RP Ltr Config Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpLtrConfigLock[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEqPh3LaneParamCm[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEqPh3LaneParamCp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_PARAM. Coefficient C-1.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieSwEqCoeffListCm[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x065D - PCIE Sw Eq CoeffList Cp</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_PCIE_EQ_PARAM. Coefficient C+1.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieSwEqCoeffListCp[5];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0662 - PCIE Disable RootPort Clock Gating</span><br><span style="color: hsl(120, 100%, 40%);">+ Describes whether the PCI Express Clock Gating for each root port is enabled by</span><br><span style="color: hsl(120, 100%, 40%);">+ platform modules. 0: Disable; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieDisableRootPortClockGating;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0663 - PCIE Enable Peer Memory Write</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether Peer Memory Writes are enabled on the platform.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEnablePeerMemoryWrite;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0664</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace17;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0665 - PCIE Compliance Test Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Compliance Test Mode shall be enabled when using Compliance Load Board.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieComplianceTestMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0666 - PCIE Rp Function Swap</span><br><span style="color: hsl(120, 100%, 40%);">+ Allows BIOS to use root port function number swapping when root port of function</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 is disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpFunctionSwap;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0667</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace18[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPmeB0S5Dis;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066A - SPI ChipSelect signal polarity</span><br><span style="color: hsl(120, 100%, 40%);">+ Selects SPI ChipSelect signal polarity.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoSpiCsPolarity[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066D - PCIE IMR</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables Isolated Memory Region for PCIe.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpImrEnabled;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066E - PCIE IMR port number</span><br><span style="color: hsl(120, 100%, 40%);">+ Selects PCIE root port number for IMR feature.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpImrSelection;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x066F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace19;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0670 - PCH Pm Wol Enable Override</span><br><span style="color: hsl(120, 100%, 40%);">+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWolEnableOverride;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if enable PCIe to wake from deep Sx.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPcieWakeFromDeepSx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0672 - PCH Pm WoW lan Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWoWlanEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the</span><br><span style="color: hsl(120, 100%, 40%);">+ PWRM_CFG3 register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWoWlanDeepSxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx</span><br><span style="color: hsl(120, 100%, 40%);">+ Determine if enable LAN to wake from deep Sx.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmLanWakeFromDeepSx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0675 - PCH Pm Deep Sx Pol</span><br><span style="color: hsl(120, 100%, 40%);">+ Deep Sx Policy.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDeepSxPol;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0676 - PCH Pm Slp S3 Min Assert</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS3MinAssert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0677 - PCH Pm Slp S4 Min Assert</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS4MinAssert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0678 - PCH Pm Slp Sus Min Assert</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpSusMinAssert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0679 - PCH Pm Slp A Min Assert</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpAMinAssert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067A - SLP_S0# Override</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'</span><br><span style="color: hsl(120, 100%, 40%);">+ will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion</span><br><span style="color: hsl(120, 100%, 40%);">+ when debug is enabled. \n</span><br><span style="color: hsl(120, 100%, 40%);">+ Note: This BIOS option should keep 'Auto', other options are intended for advanced </span><br><span style="color: hsl(120, 100%, 40%);">+ configuration only.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:Enabled, 2:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0Override;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067B - S0ix Override Settings</span><br><span style="color: hsl(120, 100%, 40%);">+ Select 'Auto', it will be auto-configured according to probe type. 'No Change' will</span><br><span style="color: hsl(120, 100%, 40%);">+ keep PMC default settings. Or select the desired debug probe type for S0ix Override</span><br><span style="color: hsl(120, 100%, 40%);">+ settings.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Reminder: DCI OOB (aka BSSB) uses CCA probe.\n</span><br><span style="color: hsl(120, 100%, 40%);">+ Note: This BIOS option should keep 'Auto', other options are intended for advanced </span><br><span style="color: hsl(120, 100%, 40%);">+ configuration only.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SlpS0DisQForDebug;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067C - USB Overcurrent Override for DbC</span><br><span style="color: hsl(120, 100%, 40%);">+ This option overrides USB Over Current enablement state that USB OC will be disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEnableDbcObs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x067D</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace20[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0680 - PCH Pm Lpc Clock Run</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether or not the LPC ClockRun feature of PCH should be enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ Default value is Disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmLpcClockRun;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0681 - PCH Pm Slp Strch Sus Up</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SLP_X Stretching After SUS Well Power Up.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpStrchSusUp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0682 - PCH Pm Slp Lan Low Dc</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable SLP_LAN# Low on DC Power.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpLanLowDc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0683 - PCH Pm Pwr Btn Override Period</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPwrBtnOverridePeriod;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown</span><br><span style="color: hsl(120, 100%, 40%);">+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableDsxAcPresentPulldown;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0685</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace21;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0686 - PCH Pm Disable Native Power Button</span><br><span style="color: hsl(120, 100%, 40%);">+ Power button native mode disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableNativePowerButton;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0687 - PCH Pm Slp S0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmSlpS0Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0688 - PCH Pm ME_WAKE_STS</span><br><span style="color: hsl(120, 100%, 40%);">+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmMeWakeSts;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS</span><br><span style="color: hsl(120, 100%, 40%);">+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmWolOvrWkSts;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068A - PCH Pm Reset Power Cycle Duration</span><br><span style="color: hsl(120, 100%, 40%);">+ Could be customized in the unit of second. Please refer to EDS for all support settings.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPwrCycDur;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068B - PCH Pm Pcie Pll Ssc</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No</span><br><span style="color: hsl(120, 100%, 40%);">+ BIOS override.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmPciePllSsc;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068C</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace22;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068D - PCH Sata Pwr Opt Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ SATA Power Optimizer on PCH side.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPwrOptEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068E - PCH Sata eSATA Speed Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EsataSpeedLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x068F - PCH Sata Speed Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataSpeedLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0690 - Enable SATA Port HotPlug</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port HotPlug.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsHotPlug[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0698 - Enable SATA Port Interlock Sw</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port Interlock Sw.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsInterlockSw[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06A0 - Enable SATA Port External</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SATA Port External.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsExternal[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06A8 - Enable SATA Port SpinUp</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the COMRESET initialization Sequence to the device.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsSpinUp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06B0 - Enable SATA Port Solid State Drive</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: HDD; 1: SSD.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsSolidStateDrive[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06B8 - Enable SATA Port Enable Dito Config</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsEnableDitoConfig[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06C0 - Enable SATA Port DmVal</span><br><span style="color: hsl(120, 100%, 40%);">+ DITO multiplier. Default is 15.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsDmVal[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06C8 - Enable SATA Port DmVal</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVSLP Idle Timeout (DITO), Default is 625.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SataPortsDitoVal[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06D8 - Enable SATA Port ZpOdd</span><br><span style="color: hsl(120, 100%, 40%);">+ Support zero power ODD.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataPortsZpOdd[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E0 - PCH Sata Rst Raid Device Id</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable RAID Alternate ID.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Client, 1:Alternate, 2:Server</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaidDeviceId;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E1 - PCH Sata Rst Raid0</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID0.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E2 - PCH Sata Rst Raid1</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID1.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E3 - PCH Sata Rst Raid10</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID10.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid10;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E4 - PCH Sata Rst Raid5</span><br><span style="color: hsl(120, 100%, 40%);">+ RAID5.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstRaid5;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E5 - PCH Sata Rst Irrt</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Rapid Recovery Technology.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstIrrt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner</span><br><span style="color: hsl(120, 100%, 40%);">+ OROM UI and BANNER.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOromUiBanner;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOromUiDelay;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates that the HDD password unlock in the OS is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstHddUnlock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06E9 - PCH Sata Rst Led Locate</span><br><span style="color: hsl(120, 100%, 40%);">+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is</span><br><span style="color: hsl(120, 100%, 40%);">+ enabled on the OS.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstLedLocate;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EA - PCH Sata Rst Irrt Only</span><br><span style="color: hsl(120, 100%, 40%);">+ Allow only IRRT drives to span internal and external ports.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstIrrtOnly;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EB - PCH Sata Rst Smart Storage</span><br><span style="color: hsl(120, 100%, 40%);">+ RST Smart Storage caching Bit.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstSmartStorage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Intel RST for PCIe Storage remapping.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieEnable[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieStoragePort[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstPcieDeviceResetDelay[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F5 - Enable eMMC HS400 Training</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400TuningRequired;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F6 - Set HS400 Tuning Data Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Set if HS400 Tuning Data Valid.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400DllDataValid;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F7 - Rx Strobe Delay Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F8 - Tx Data Delay Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06F9 - I/O Driver Strength</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:33 Ohm, 1:40 Ohm, 2:50 Ohm</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchScsEmmcHs400DriverStrength;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x06FA - PCH SerialIo I2C Pads Termination</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5</span><br><span style="color: hsl(120, 100%, 40%);">+ pads termination respectively. One byte for each controller, byte0 for I2C0, byte1</span><br><span style="color: hsl(120, 100%, 40%);">+ for I2C1, and so on.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSerialIoI2cPadsTermination[6];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0700</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace23;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0701 - PcdSerialIoUart0PinMuxing</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:default pins, 1:pins muxed with CNV_BRI/RGI</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoUart0PinMuxing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0702</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace24[1];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines</span><br><span style="color: hsl(120, 100%, 40%);">+ Enables UART hardware flow control, CTS and RTS linesh.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoUartHwFlowCtrl[3];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0706 - UART Number For Debug Purpose</span><br><span style="color: hsl(120, 100%, 40%);">+ UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected</span><br><span style="color: hsl(120, 100%, 40%);">+ as CNVi BT Core interface, it cannot be used for debug purpose.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:UART0, 1:UART1, 2:UART2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoDebugUartNumber;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0707 - Enable Debug UART Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable debug UART controller after post.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SerialIoEnableDebugUartAfterPost;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0708 - Enable Serial IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+ Determines if enable Serial IRQ.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSirqEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0709 - Serial IRQ Mode Select</span><br><span style="color: hsl(120, 100%, 40%);">+ Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSirqMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070A - Start Frame Pulse Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchStartFramePulse;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070B - Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedForFuture1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070C - Thermal Device SMI Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ This locks down SMI Enable on Alert Thermal Sensor Trip.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTsmicLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070D - Thermal Throttling Custimized T0Level Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T0Level value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT0Level;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x070F - Thermal Throttling Custimized T1Level Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T1Level value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT1Level;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Custimized T2Level value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchT2Level;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0713 - Enable The Thermal Throttle</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable the thermal throttle function.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0714 - PMSync State 13</span><br><span style="color: hsl(120, 100%, 40%);">+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force</span><br><span style="color: hsl(120, 100%, 40%);">+ at least T2 state.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTState13Enable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0715 - Thermal Throttle Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Throttle Lock.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchTTLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0716 - Thermal Throttling Suggested Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Throttling Suggested Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TTSuggestedSetting;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0717 - Enable PCH Cross Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable PCH Cross Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TTCrossThrottling;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ DMI Thermal Sensor Autonomous Width Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiTsawEn;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ DMT thermal sensor suggested representative values.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiSuggestedSetting;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071A - Thermal Sensor 0 Target Width</span><br><span style="color: hsl(120, 100%, 40%);">+ DMT thermal sensor suggested representative values.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS0TW;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071B - Thermal Sensor 1 Target Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 1 Target Width.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS1TW;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071C - Thermal Sensor 2 Target Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 2 Target Width.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS2TW;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071D - Thermal Sensor 3 Target Width</span><br><span style="color: hsl(120, 100%, 40%);">+ Thermal Sensor 3 Target Width.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiTS3TW;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071E - Port 0 T1 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T1 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T1M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x071F - Port 0 T2 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T2 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T2M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0720 - Port 0 T3 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 T3 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0T3M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0721 - Port 0 Tdispatch</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Tdispatch.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0TDisp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0722 - Port 1 T1 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T1 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T1M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0723 - Port 1 T2 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T2 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T2M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0724 - Port 1 T3 Multipler</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 T3 Multipler.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1T3M;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0725 - Port 1 Tdispatch</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Tdispatch.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1TDisp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0726 - Port 0 Tinactive</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Tinactive.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0Tinact;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 0 Alternate Fast Init Tdispatch.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP0TDispFinit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0728 - Port 1 Tinactive</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Tinactive.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1Tinact;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch</span><br><span style="color: hsl(120, 100%, 40%);">+ Port 1 Alternate Fast Init Tdispatch.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataP1TDispFinit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072A - Sata Thermal Throttling Suggested Setting</span><br><span style="color: hsl(120, 100%, 40%);">+ Sata Thermal Throttling Suggested Setting.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataThermalSuggestedSetting;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072B - Enable Memory Thermal Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryThrottlingEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072C - Memory Thermal Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryPmsyncEnable[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x072E - Enable Memory Thermal Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryC0TransmitEnable[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0730 - Enable Memory Thermal Throttling</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable Memory Thermal Throttling.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchMemoryPinSelection[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0732 - Thermal Device Temperature</span><br><span style="color: hsl(120, 100%, 40%);">+ Decides the temperature.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchTemperatureHotLevel;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0734 - Enable xHCI Compliance Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Compliance Mode can be enabled for testing through this option but this is disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ by default.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchEnableComplianceMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0735 - USB2 Port Over Current Pin</span><br><span style="color: hsl(120, 100%, 40%);">+ Describe the specific over current pin number of USB 2.0 Port N.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2OverCurrentPin[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0745 - USB3 Port Over Current Pin</span><br><span style="color: hsl(120, 100%, 40%);">+ Describe the specific over current pin number of USB 3.0 Port N.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb3OverCurrentPin[10];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x074F - Enable 8254 Static Clock Gating</span><br><span style="color: hsl(120, 100%, 40%);">+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time</span><br><span style="color: hsl(120, 100%, 40%);">+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support</span><br><span style="color: hsl(120, 100%, 40%);">+ boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Enable8254ClockGating;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0750 - PCH Sata Rst Optane Memory</span><br><span style="color: hsl(120, 100%, 40%);">+ Optane Memory</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstOptaneMemory;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage</span><br><span style="color: hsl(120, 100%, 40%);">+ CPU Attached Storage</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstCpuAttachedStorage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0752</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace25[2];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0754 - Pch PCIE device override table pointer</span><br><span style="color: hsl(120, 100%, 40%);">+ The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span style="color: hsl(120, 100%, 40%);">+ is a pointer points to a 32bit address. And it's only used in PostMem phase. Please</span><br><span style="color: hsl(120, 100%, 40%);">+ refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId</span><br><span style="color: hsl(120, 100%, 40%);">+ must be 0.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PchPcieDeviceOverrideTablePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0758 - Enable TCO timer.</span><br><span style="color: hsl(120, 100%, 40%);">+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have</span><br><span style="color: hsl(120, 100%, 40%);">+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer</span><br><span style="color: hsl(120, 100%, 40%);">+ emulation must be enabled, and WDAT table must not be exposed to the OS.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableTcoTimer;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0759 - BgpdtHash[4]</span><br><span style="color: hsl(120, 100%, 40%);">+ BgpdtHash values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 BgpdtHash[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0779 - BiosGuardAttr</span><br><span style="color: hsl(120, 100%, 40%);">+ BiosGuardAttr default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BiosGuardAttr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x077D - BiosGuardModulePtr</span><br><span style="color: hsl(120, 100%, 40%);">+ BiosGuardModulePtr default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 BiosGuardModulePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0785 - SendEcCmd</span><br><span style="color: hsl(120, 100%, 40%);">+ SendEcCmd function pointer. \n</span><br><span style="color: hsl(120, 100%, 40%);">+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE </span><br><span style="color: hsl(120, 100%, 40%);">+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SendEcCmd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078D - EcCmdProvisionEav</span><br><span style="color: hsl(120, 100%, 40%);">+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EcCmdProvisionEav;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078E - EcCmdLock</span><br><span style="color: hsl(120, 100%, 40%);">+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EcCmdLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x078F - SgxEpoch0</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxEpoch0 default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxEpoch0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0797 - SgxEpoch1</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxEpoch1 default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 SgxEpoch1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x079F - SgxSinitNvsData</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxSinitNvsData default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxSinitNvsData;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A0 - Si Config CSM Flag.</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform specific common policies that used by several silicon components. CSM status flag.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SiCsmFlag;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A1</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 SiSsidTablePtr;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A5</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 SiNumberOfSsidTableEntry;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A7 - SATA RST Interrupt Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Msix, 1:Msi, 2:Legacy</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstInterrupt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A8 - ME Unconfig on RTC clear</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ 2: Cmos is clear, status unkonwn. 3: Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos</span><br><span style="color: hsl(120, 100%, 40%);">+ is clear, 3: Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MeUnconfigOnRtcClear;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07A9 - Enable PS_ON.</span><br><span style="color: hsl(120, 100%, 40%);">+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power</span><br><span style="color: hsl(120, 100%, 40%);">+ target that will be required by the California Energy Commission (CEC). When FALSE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PS_ON is to be disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsOnEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO</span><br><span style="color: hsl(120, 100%, 40%);">+ and VccSTG rails instead of SLP_S0# pin.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmcCpuC10GatePinEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AB - Pch Dmi Aspm Ctrl</span><br><span style="color: hsl(120, 100%, 40%);">+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b></span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchDmiAspmCtrl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AC</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[1];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S Test Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Signature;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B1 - Enable/Disable Device 7 </span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Device 7 enabled, Disable (Default): Device 7 disabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChapDeviceEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B2 - Skip PAM register lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM registers will be locked by RC</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipPamLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B3 - EDRAM Test Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):</span><br><span style="color: hsl(120, 100%, 40%);">+ PAM registers will be locked by RC</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EdramTestMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B4 - DMI Extended Sync Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended</span><br><span style="color: hsl(120, 100%, 40%);">+ Sync Control</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiExtSync;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B5 - DMI IOT Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DmiIot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07B6 - PEG Max Payload size per root port</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PegMaxPayload[4];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BA - Enable/Disable IGFX RenderStandby</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RenderStandby;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BB - Enable/Disable IGFX PmSupport</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmSupport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BC - Enable/Disable CdynmaxClamp</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CdynmaxClampEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BD - Disable VT-d</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VtdDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BE - GT Frequency Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:</span><br><span style="color: hsl(120, 100%, 40%);">+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18: 1200 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:</span><br><span style="color: hsl(120, 100%, 40%);">+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x18: 1200 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GtFreqMax;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07BF - Disable Turbo GT</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableTurboGt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07C0 - SaPostMemTestRsvd</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for SA Post-Mem Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SaPostMemTestRsvd[11];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CB - 1-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,</span><br><span style="color: hsl(120, 100%, 40%);">+ 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 OneCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CC - 2-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TwoCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CD - 3-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThreeCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CE - 4-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FourCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07CF - Enable or Disable HWP</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b></span><br><span style="color: hsl(120, 100%, 40%);">+ 2-3:Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Hwp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D0 - Hardware Duty Cycle Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HdcControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D1 - Package Long duration turbo mode time</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit1Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D2 - Short Duration Turbo Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D3 - Turbo settings Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TurboPowerLimitLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D4 - Package PL3 time window</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 time window range for this policy from 0 to 64ms</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D5 - Package PL3 Duty Cycle</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 Duty Cycle; Valid Range is 0 to 100</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3DutyCycle;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D6 - Package PL3 Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit3Lock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D7 - Package PL4 Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PowerLimit4Lock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D8 - TCC Activation Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ TCC Activation Offset. Offset from factory set TCC activation temperature at which</span><br><span style="color: hsl(120, 100%, 40%);">+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation</span><br><span style="color: hsl(120, 100%, 40%);">+ Temperature, in volts.For Y SKU, the recommended default for this policy is <b>10</b>,</span><br><span style="color: hsl(120, 100%, 40%);">+ For all other SKUs the recommended default are <b>0</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccActivationOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle</span><br><span style="color: hsl(120, 100%, 40%);">+ below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,</span><br><span style="color: hsl(120, 100%, 40%);">+ For all other SKUs the recommended default are <b>0: Disabled</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccOffsetClamp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DA - Tcc Offset Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature</span><br><span style="color: hsl(120, 100%, 40%);">+ target; 0: Disabled; <b>1: Enabled </b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TccOffsetLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DB - Custom Ratio State Entries</span><br><span style="color: hsl(120, 100%, 40%);">+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio table.Sets the number of custom P-states. At least 2 states must be present</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 NumberOfEntries;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DC - Custom Short term Power Limit time window</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1PowerLimit1Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DD - Custom Turbo Activation Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1TurboActivationRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DE - Custom Config Tdp Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom1ConfigTdpControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07DF - Custom Short term Power Limit time window</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2PowerLimit1Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E0 - Custom Turbo Activation Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2TurboActivationRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E1 - Custom Config Tdp Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom2ConfigTdpControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E2 - Custom Short term Power Limit time window</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3PowerLimit1Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E3 - Custom Turbo Activation Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3TurboActivationRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E4 - Custom Config Tdp Control</span><br><span style="color: hsl(120, 100%, 40%);">+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Custom3ConfigTdpControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E5 - ConfigTdp mode settings Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E6 - Load Configurable TDP SSDT</span><br><span style="color: hsl(120, 100%, 40%);">+ Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpBios;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E7 - PL1 Enable value</span><br><span style="color: hsl(120, 100%, 40%);">+ PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E8 - PL1 timewindow</span><br><span style="color: hsl(120, 100%, 40%);">+ PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16</span><br><span style="color: hsl(120, 100%, 40%);">+ , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit1Time;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07E9 - PL2 Enable Value</span><br><span style="color: hsl(120, 100%, 40%);">+ PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PsysPowerLimit2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MlcStreamerPrefetcher;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MlcSpatialPrefetcher;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MonitorMwaitEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07ED - Enable or Disable initialization of machine check registers</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MachineCheckEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EE - Enable or Disable processor debug features</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DebugInterfaceEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07EF - Lock or Unlock debug interface features</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DebugInterfaceLockEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI</span><br><span style="color: hsl(120, 100%, 40%);">+ AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ApIdleManner;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F1 - Control on Processor Trace output scheme</span><br><span style="color: hsl(120, 100%, 40%);">+ Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Single Range Output, 1: ToPA Output</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcessorTraceOutputScheme;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F2 - Enable or Disable Processor Trace feature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcessorTraceEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07F3 - Base of memory region allocated for Processor Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ Base address of memory region allocated for Processor Trace. Processor Trace requires</span><br><span style="color: hsl(120, 100%, 40%);">+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 ProcessorTraceMemBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07FB - Memory region allocation for Processor Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ Length in bytes of memory region allocated for Processor Trace. Processor Trace</span><br><span style="color: hsl(120, 100%, 40%);">+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b></span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 ProcessorTraceMemLength;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07FF - Enable or Disable Voltage Optimization feature</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VoltageOptimization;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Eist;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0801 - Enable or Disable Energy Efficient P-state</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnergyEfficientPState;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnergyEfficientTurbo;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0803 - Enable or Disable T states</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable T states; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TStates;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 BiProcHot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableProcHotOut;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0806 - Enable or Disable PROCHOT# Response</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcHotResponse;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0807 - Enable or Disable VR Thermal Alert</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableVrThermalAlert;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0808 - Enable or Disable Thermal Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 AutoThermalReporting;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0809 - Enable or Disable Thermal Monitor</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThermalMonitor;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080A - Enable or Disable CPU power states (C-states)</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Cx;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080B - Configure C-State Configuration Lock</span><br><span style="color: hsl(120, 100%, 40%);">+ Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PmgCstCfgCtrlLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080C - Enable or Disable Enhanced C-states</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1e;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080D - Enable or Disable Package Cstate Demotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateUnDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x080F - Enable or Disable CState-Pre wake</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CStatePreWake;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0810 - Enable or Disable TimedMwait Support.</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TimedMwait;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstCfgCtrIoMwaitRedirection;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0812 - Set the Max Pkg Cstate</span><br><span style="color: hsl(120, 100%, 40%);">+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep</span><br><span style="color: hsl(120, 100%, 40%);">+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,</span><br><span style="color: hsl(120, 100%, 40%);">+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PkgCStateLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0813 - TimeUnit for C-State Latency Control0</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl0TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0814 - TimeUnit for C-State Latency Control1</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl1TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0815 - TimeUnit for C-State Latency Control2</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl2TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0816 - TimeUnit for C-State Latency Control3</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl3TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0817 - TimeUnit for C-State Latency Control4</span><br><span style="color: hsl(120, 100%, 40%);">+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl4TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0818 - TimeUnit for C-State Latency Control5</span><br><span style="color: hsl(120, 100%, 40%);">+ TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns</span><br><span style="color: hsl(120, 100%, 40%);">+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CstateLatencyControl5TimeUnit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0819 - Interrupt Redirection Mode Select</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:</span><br><span style="color: hsl(120, 100%, 40%);">+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PpmIrmSetting;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081A - Lock prochot configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcHotLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081B - Configuration for boot TDP selection</span><br><span style="color: hsl(120, 100%, 40%);">+ Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP</span><br><span style="color: hsl(120, 100%, 40%);">+ Up;0xFF : Deactivate</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ConfigTdpLevel;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081C - Race To Halt</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled</span><br><span style="color: hsl(120, 100%, 40%);">+ through MSR 1FC bit 20)Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RaceToHalt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081D - Max P-State Ratio</span><br><span style="color: hsl(120, 100%, 40%);">+ Max P-State Ratio, Valid Range 0 to 0x7F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MaxRatio;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x081E - P-state ratios for custom P-state table</span><br><span style="color: hsl(120, 100%, 40%);">+ P-state ratios for custom P-state table. NumberOfEntries has valid range between</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]</span><br><span style="color: hsl(120, 100%, 40%);">+ are configurable. Valid Range of each entry is 0 to 0x7F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 StateRatio[40];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table</span><br><span style="color: hsl(120, 100%, 40%);">+ P-state ratios for max 16 version of custom P-state table. This table is used for</span><br><span style="color: hsl(120, 100%, 40%);">+ OS versions limited to a max of 16 P-States. If the first entry of this table is</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and</span><br><span style="color: hsl(120, 100%, 40%);">+ up to the top 16 values of the StateRatio table will be used instead. Valid Range</span><br><span style="color: hsl(120, 100%, 40%);">+ of each entry is 0 to 0x7F</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 StateRatioMax16[16];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0856 - Platform Power Pmax</span><br><span style="color: hsl(120, 100%, 40%);">+ PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0-1024 Watts. Value of 800 = 100W</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PsysPmax;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl0Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl1Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl2Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl3Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl4Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 CstateLatencyControl5Irtl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0864 - Package Long duration turbo mode power limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.</span><br><span style="color: hsl(120, 100%, 40%);">+ Valid Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0868 - Package Short duration turbo mode power limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit2Power;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x086C - Package PL3 power limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0870 - Package PL4 power limit</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PowerLimit4;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0874 - Tcc Offset Time Window for RATL</span><br><span style="color: hsl(120, 100%, 40%);">+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TccOffsetTimeWindowForRatl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom1PowerLimit1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom1PowerLimit2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom2PowerLimit1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom2PowerLimit2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom3PowerLimit1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Custom3PowerLimit2;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0890 - Platform PL1 power</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PsysPowerLimit1Power;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0894 - Platform PL2 power</span><br><span style="color: hsl(120, 100%, 40%);">+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PsysPowerLimit2Power;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0898 - Set Three Strike Counter Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ False (default): Three Strike counter will be incremented and True: Prevents Three</span><br><span style="color: hsl(120, 100%, 40%);">+ Strike counter from incrementing; <b>0: False</b>; 1: True.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: False, 1: True</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ThreeStrikeCounterDisable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT</span><br><span style="color: hsl(120, 100%, 40%);">+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 HwpInterruptControl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089A - 5-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 FiveCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089B - 6-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SixCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089C - 7-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SevenCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089D - 8-Core Ratio Limit</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(120, 100%, 40%);">+ to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0:0xFF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EightCoreRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableItbm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EnableItbmDriver;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1StateAutoDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C1StateUnDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A2 - CpuWakeUpTimer</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased</span><br><span style="color: hsl(120, 100%, 40%);">+ to 180 seconds. 0: Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 CpuWakeUpTimer;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A3 - Minimum Ring ratio limit override</span><br><span style="color: hsl(120, 100%, 40%);">+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio limit</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MinRingRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A4 - Minimum Ring ratio limit override</span><br><span style="color: hsl(120, 100%, 40%);">+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo</span><br><span style="color: hsl(120, 100%, 40%);">+ ratio limit</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MaxRingRatioLimit;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateAutoDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateUnDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A7 - ReservedCpuPostMemTest</span><br><span style="color: hsl(120, 100%, 40%);">+ Reserved for CPU Post-Mem Test</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemTest[19];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BA - SgxSinitDataFromTpm</span><br><span style="color: hsl(120, 100%, 40%);">+ SgxSinitDataFromTpm default values</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SgxSinitDataFromTpm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BB - End of Post message</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):</span><br><span style="color: hsl(120, 100%, 40%);">+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 EndOfPostMessage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BC - D0I3 Setting for HECI Disable</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all</span><br><span style="color: hsl(120, 100%, 40%);">+ HECI devices</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DisableD0I3SettingForHeci;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BD - HD Audio Reset Wait Timer</span><br><span style="color: hsl(120, 100%, 40%);">+ The delay timer after Azalia reset, the value is number of microseconds. Default is 600.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PchHdaResetWaitTimer;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08BF - Enable LOCKDOWN SMI</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownGlobalSmi;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchLockDownBiosInterface;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C1 - Unlock all GPIO pads</span><br><span style="color: hsl(120, 100%, 40%);">+ Force all GPIO pads to be unlocked for debug purpose.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchUnlockGpioPads;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C2 - PCH Unlock SBI access</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSbiUnlock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C3 - PCH Unlock SideBand access</span><br><span style="color: hsl(120, 100%, 40%);">+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before</span><br><span style="color: hsl(120, 100%, 40%);">+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchSbAccessUnlock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Max Snoop Latency.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpLtrMaxSnoopLatency[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Max Non-Snoop Latency.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Mode.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSnoopLatencyOverrideMode[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0954 - PCIE RP Snoop Latency Override Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Snoop Latency Override Value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpSnoopLatencyOverrideValue[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies scale used for slot power limit value. Leave as 0 to set to default.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpSlotPowerLimitScale[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x09FC - PCIE RP Slot Power Limit Value</span><br><span style="color: hsl(120, 100%, 40%);">+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 PcieRpSlotPowerLimitValue[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset</span><br><span style="color: hsl(120, 100%, 40%);">+ Used during Gen3 Link Equalization. Used for all lanes. Default is 5.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpUptp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset</span><br><span style="color: hsl(120, 100%, 40%);">+ Used during Gen3 Link Equalization. Used for all lanes. Default is 7.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieRpDptp[24];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode</span><br><span style="color: hsl(120, 100%, 40%);">+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcieEnablePort8xhDecode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5D - PCIE Port8xh Decode Port Index</span><br><span style="color: hsl(120, 100%, 40%);">+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPciePort8xhDecodePortIndex;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5E - PCH Energy Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ Disable/Enable PCH to CPU energy report feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchPmDisableEnergyReport;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A5F - PCH Sata Test Mode</span><br><span style="color: hsl(120, 100%, 40%);">+ Allow entrance to the PCH SATA test modes.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataTestMode;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable</span><br><span style="color: hsl(120, 100%, 40%);">+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning</span><br><span style="color: hsl(120, 100%, 40%);">+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PchXhciOcLock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A61</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace26[17];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A72 - Skip POSTBOOT SAI</span><br><span style="color: hsl(120, 100%, 40%);">+ Deprecated</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SkipPostBootSai;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A73 - Mctp Broadcast Cycle</span><br><span style="color: hsl(120, 100%, 40%);">+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MctpBroadcastCycle;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A74</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsTestUpd[12];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_S_TEST_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp S UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_CONFIG FspsConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x07AD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_TEST_CONFIG FspsTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0A80</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPS_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h</span><br><span>new file mode 100644</span><br><span>index 0000000..eeba7ae</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h</span><br><span>@@ -0,0 +1,136 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(120, 100%, 40%);">+are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer.</span><br><span style="color: hsl(120, 100%, 40%);">+* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(120, 100%, 40%);">+ list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ other materials provided with the distribution.</span><br><span style="color: hsl(120, 100%, 40%);">+* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(120, 100%, 40%);">+ be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(120, 100%, 40%);">+ specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(120, 100%, 40%);">+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(120, 100%, 40%);">+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(120, 100%, 40%);">+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(120, 100%, 40%);">+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(120, 100%, 40%);">+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(120, 100%, 40%);">+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(120, 100%, 40%);">+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(120, 100%, 40%);">+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(120, 100%, 40%);">+ THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __FSPTUPD_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <FspUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Core UPD</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0024</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MicrocodeRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0028</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CodeRegionBase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x002C</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 CodeRegionSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0030</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[16];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_CORE_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040 - PcdSerialIoUartDebugEnable</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. </span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUartDebugEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT</span><br><span style="color: hsl(120, 100%, 40%);">+ Core interface, it cannot be used for debug purpose.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUartNumber;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT</span><br><span style="color: hsl(120, 100%, 40%);">+ Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is</span><br><span style="color: hsl(120, 100%, 40%);">+ set to UART0.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:default pins, 1:pins muxed with CNV_BRI/RGI</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 PcdSerialIoUart0PinMuxing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0043</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0044</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcdSerialIoUartInputClock;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0048 - Pci Express Base Address</span><br><span style="color: hsl(120, 100%, 40%);">+ Base address to be programmed for Pci Express </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT64 PcdPciExpressBaseAddress;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0050 - Pci Express Region Length</span><br><span style="color: hsl(120, 100%, 40%);">+ Region Length to be programmed for Pci Express </span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PcdPciExpressRegionLength;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0054</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFsptUpd1[44];</span><br><span style="color: hsl(120, 100%, 40%);">+} FSP_T_CONFIG;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Fsp T UPD Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0000</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_UPD_HEADER FspUpdHeader;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0020</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSPT_CORE_UPD FsptCoreUpd;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0040</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_T_CONFIG FsptConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0080</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 UpdTerminator;</span><br><span style="color: hsl(120, 100%, 40%);">+} FSPT_UPD;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h</span><br><span>new file mode 100644</span><br><span>index 0000000..e2a3e09</span><br><span>--- /dev/null</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h</span><br><span>@@ -0,0 +1,288 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file
</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains definitions required for creation of
</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory S3 Save data, Memory Info data and Memory Platform
</span><br><span style="color: hsl(120, 100%, 40%);">+ data hobs.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+@copyright
</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL CONFIDENTIAL
</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright 1999 - 2018 Intel Corporation.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ The source code contained or described herein and all documents related to the
</span><br><span style="color: hsl(120, 100%, 40%);">+ source code ("Material") are owned by Intel Corporation or its suppliers or
</span><br><span style="color: hsl(120, 100%, 40%);">+ licensors. Title to the Material remains with Intel Corporation or its suppliers
</span><br><span style="color: hsl(120, 100%, 40%);">+ and licensors. The Material may contain trade secrets and proprietary and
</span><br><span style="color: hsl(120, 100%, 40%);">+ confidential information of Intel Corporation and its suppliers and licensors,
</span><br><span style="color: hsl(120, 100%, 40%);">+ and is protected by worldwide copyright and trade secret laws and treaty
</span><br><span style="color: hsl(120, 100%, 40%);">+ provisions. No part of the Material may be used, copied, reproduced, modified,
</span><br><span style="color: hsl(120, 100%, 40%);">+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
</span><br><span style="color: hsl(120, 100%, 40%);">+ without Intel's prior express written permission.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ No license under any patent, copyright, trade secret or other intellectual
</span><br><span style="color: hsl(120, 100%, 40%);">+ property right is granted to or conferred upon you by disclosure or delivery
</span><br><span style="color: hsl(120, 100%, 40%);">+ of the Materials, either expressly, by implication, inducement, estoppel or
</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise. Any license under such intellectual property rights must be
</span><br><span style="color: hsl(120, 100%, 40%);">+ express and approved by Intel in writing.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ Unless otherwise agreed by Intel in writing, you may not remove or alter
</span><br><span style="color: hsl(120, 100%, 40%);">+ this notice or any other notice embedded in Materials by Intel or
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel's suppliers or licensors in any way.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
</span><br><span style="color: hsl(120, 100%, 40%);">+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms of your license agreement with Intel or your vendor. This file may
</span><br><span style="color: hsl(120, 100%, 40%);">+ be modified by the user, subject to additional terms of the license agreement.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+@par Specification Reference:
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MEM_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MEM_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (push, 1)
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryS3DataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryInfoDataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryPlatformDataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_NODE 1
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_CH 2
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_DIMM 2
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Host reset states from MRC.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+#define WARM_BOOT 2
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_MC_CHNL_RANK_PRESENT 0x7C
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK0_PRS BIT0
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK1_PRS BIT1
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK2_PRS BIT4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK3_PRS BIT5
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Defines taken from MRC so avoid having to include MrcInterface.h
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MAX_SPD_SAVE define in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAX_SPD_SAVE
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_SPD_SAVE 29
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// MRC version description.
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Major; ///< Major version number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Minor; ///< Minor version number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rev; ///< Revision number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Build; ///< Build number
</span><br><span style="color: hsl(120, 100%, 40%);">+} SiMrcVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcChannelSts enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_NOT_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_DISABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDimmSts enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_ENABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_DISABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_NOT_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcBootMode enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmCold
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmCold 0 // Cold boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmWarm
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmWarm 1 // Warm boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmS3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmS3 2 // S3 resume
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmFast
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmFast 3 // Fast boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDdrType enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR4 0
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR3 1
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR3 2
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CPU_CFL//CNL
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR4 3
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#else//CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_UNKNOWN
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_UNKNOWN 3
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif//CPU_CFL-endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// DIMM timings
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_CH_TIMING;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_TA_TIMING;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Memory SMBIOS & OC Memory Data Hob
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MfgId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+} DIMM_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this channel should be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
</span><br><span style="color: hsl(120, 100%, 40%);">+} CHANNEL_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this controller should be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+} CONTROLLER_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec
</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.18.2 and Table 75
</span><br><span style="color: hsl(120, 100%, 40%);">+ **/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec
</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.17.3 and Table 72
</span><br><span style="color: hsl(120, 100%, 40%);">+ **/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ErrorCorrectionType;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiMrcVersion Version;
</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOLEAN EccSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryProfile;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TotalPhysicalMemorySize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ratio;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RefClk;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VddVoltage[MAX_PROFILE_NUM];
</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTROLLER_INFO Controller[MAX_NODE];
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_INFO_DATA_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/**
</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Platform Data Hob
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 1:</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ - Initial version.
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 2:</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BootMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GttBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MmioSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PciEBaseAddress;
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef CPU_CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif //CPU_CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE EfiHobGuidType;
</span><br><span style="color: hsl(120, 100%, 40%);">+ MEMORY_PLATFORM_DATA Data;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 *Buffer;
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (pop)
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _MEM_INFO_HOB_H_
</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25335">change 25335</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25335"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f </div>
<div style="display:none"> Gerrit-Change-Number: 25335 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>