[coreboot-gerrit] Change in coreboot[master]: soc/skylake/cpu: Fix Intel SpeedStep enable/disable

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/25330


Change subject: soc/skylake/cpu: Fix Intel SpeedStep enable/disable
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soc/skylake/cpu: Fix Intel SpeedStep enable/disable

In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr.  Fix by reverting to previous (simpler) implementation.

[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566

Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.

Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/skylake/cpu.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25330/1

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 6e98afa..1a2de73 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -293,9 +293,9 @@
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
 	if (conf->eist_enable)
-		cpu_enable_eist();
+		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
 	else
-		cpu_disable_eist();
+		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Gerrit-Change-Number: 25330
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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