<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25330">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/skylake/cpu: Fix Intel SpeedStep enable/disable<br><br>In an attempt at consolidation, commit 0a203d1 [1] introduced<br>an additional read/write of the MISC_ENABLE msr, as well a bug<br>which nullified the setting of Intel SpeedStep by inserting said<br>read/write calls in between another set of read/write calls to the<br>same msr.  Fix by reverting to previous (simpler) implementation.<br><br>[1] soc/intel/skylake: Use CPU common library code<br>https://review.coreboot.org/19566<br><br>Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify<br>SpeedStep bit correctly set based on devicetree setting.<br><br>Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/skylake/cpu.c<br>1 file changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25330/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c</span><br><span>index 6e98afa..1a2de73 100644</span><br><span>--- a/src/soc/intel/skylake/cpu.c</span><br><span>+++ b/src/soc/intel/skylake/cpu.c</span><br><span>@@ -293,9 +293,9 @@</span><br><span>         msr.lo |= (1 << 0);       /* Fast String enable */</span><br><span>     msr.lo |= (1 << 3);       /* TM1/TM2/EMTTM enable */</span><br><span>   if (conf->eist_enable)</span><br><span style="color: hsl(0, 100%, 40%);">-               cpu_enable_eist();</span><br><span style="color: hsl(120, 100%, 40%);">+            msr.lo |= (1 << 16);      /* Enhanced SpeedStep Enable */</span><br><span>      else</span><br><span style="color: hsl(0, 100%, 40%);">-            cpu_disable_eist();</span><br><span style="color: hsl(120, 100%, 40%);">+           msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */</span><br><span>     wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span>    /* Disable Thermal interrupts */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25330">change 25330</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25330"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9 </div>
<div style="display:none"> Gerrit-Change-Number: 25330 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>