[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25290


Change subject: [WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot
......................................................................

[WIP]soc/intel/cannonlake: Clear EMMC timeout for USB boot

Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by OS during USB boot but OS still
initializes emmc. Add _INI to cover USB boot case.

BUG=b.71586766
TEST=Install OS into EMMC

Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/cannonlake/acpi/scs.asl
1 file changed, 13 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/25290/1

diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 4062e70..7e9195a 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -31,6 +31,12 @@
 			PGEN, 1,	/* PG_ENABLE */
 		}
 
+		Method(_INI) {
+			/* Clear register 0x1C20/0x4820 */
+                        ^^PCRA (PID_EMMC, 0x1C20, 0x0)
+                        ^^PCRA (PID_EMMC, 0x4820, 0x0)
+		}
+
 		Method(_PS0, 0, Serialized) {
 			Stall (50) // Sleep 50 us
 
@@ -80,6 +86,13 @@
 			PGEN, 1,	/* PG_ENABLE */
 		}
 
+		Method(_INI)
+		{
+			/* Clear register 0x1C20/0x4820 */
+			^^PCRA (PID_SDX, 0x1C20, 0x0)
+			^^PCRA (PID_SDX, 0x4820, 0x0)
+		}
+
 		Method (_PS0, 0, Serialized)
 		{
 			Store (0, PGEN) /* Disable PG */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Gerrit-Change-Number: 25290
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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