[coreboot-gerrit] Change in coreboot[master]: intel/fsp: Update Cannonlake FSP header

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25289


Change subject: intel/fsp: Update Cannonlake FSP header
......................................................................

intel/fsp: Update Cannonlake FSP header

Update Cannonlake FSP header to version 7.x.2A.20, the following changes
had been made:
    1. Add MemtestonWarmBoot option.
    2. Add enable8254clockgatingonS3 option.
    3. Default disable Tccoffsetlock

BUG=None
TEST=None

Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
2 files changed, 21 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25289/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
index d014f81..74cc672 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
@@ -2291,9 +2291,15 @@
 **/
   UINT8                       PegImrRpSelection;
 
-/** Offset 0x0513
+/** Offset 0x0513 - Memory Test on Warm Boot
+  Run Base Memory Test on Warm Boot
+  0:Disable, 1:Enable
 **/
-  UINT8                       ReservedFspmUpd[12];
+  UINT8                       MemTestOnWarmBoot;
+
+/** Offset 0x0514
+**/
+  UINT8                       ReservedFspmUpd[11];
 } FSP_M_CONFIG;
 
 /** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 0f3577a..4daf891 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -2154,9 +2154,17 @@
 **/
   UINT8                       SataRstCpuAttachedStorage;
 
-/** Offset 0x0752
+/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
+  This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+  8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+  avoids the SMI requirement for the programming.
+  $EN_DIS
 **/
-  UINT8                       UnusedUpdSpace25[2];
+  UINT8                       Enable8254ClockGatingOnS3;
+
+/** Offset 0x0753
+**/
+  UINT8                       UnusedUpdSpace25;
 
 /** Offset 0x0754 - Pch PCIE device override table pointer
   The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -2472,7 +2480,7 @@
 
 /** Offset 0x07DA - Tcc Offset Lock
   Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
-  target; 0: Disabled; <b>1: Enabled </b>.
+  target; <b>0: Disabled</b>; 1: Enabled.
   $EN_DIS
 **/
   UINT8                       TccOffsetLock;
@@ -2886,13 +2894,13 @@
 
 /** Offset 0x0870 - Package PL4 power limit
   Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
-  Range 0 to 4095875 in Step size of 125
+  Range 0 to 1023875 in Step size of 125
 **/
   UINT32                      PowerLimit4;
 
 /** Offset 0x0874 - Tcc Offset Time Window for RATL
   Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
-  Range 0 to 4095875 in Step size of 125
+  Range 0 to 1023875 in Step size of 125
 **/
   UINT32                      TccOffsetTimeWindowForRatl;
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Gerrit-Change-Number: 25289
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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