<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25289">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp: Update Cannonlake FSP header<br><br>Update Cannonlake FSP header to version 7.x.2A.20, the following changes<br>had been made:<br> 1. Add MemtestonWarmBoot option.<br> 2. Add enable8254clockgatingonS3 option.<br> 3. Default disable Tccoffsetlock<br><br>BUG=None<br>TEST=None<br><br>Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>2 files changed, 21 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25289/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>index d014f81..74cc672 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h</span><br><span>@@ -2291,9 +2291,15 @@</span><br><span> **/</span><br><span> UINT8 PegImrRpSelection;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0513</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0513 - Memory Test on Warm Boot</span><br><span style="color: hsl(120, 100%, 40%);">+ Run Base Memory Test on Warm Boot</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disable, 1:Enable</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmUpd[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemTestOnWarmBoot;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0514</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[11];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span> /** Fsp M Test Configuration</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>index 0f3577a..4daf891 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>@@ -2154,9 +2154,17 @@</span><br><span> **/</span><br><span> UINT8 SataRstCpuAttachedStorage;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0752</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3</span><br><span style="color: hsl(120, 100%, 40%);">+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the</span><br><span style="color: hsl(120, 100%, 40%);">+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This</span><br><span style="color: hsl(120, 100%, 40%);">+ avoids the SMI requirement for the programming.</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace25[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Enable8254ClockGatingOnS3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0753</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace25;</span><br><span> </span><br><span> /** Offset 0x0754 - Pch PCIE device override table pointer</span><br><span> The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span>@@ -2472,7 +2480,7 @@</span><br><span> </span><br><span> /** Offset 0x07DA - Tcc Offset Lock</span><br><span> Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature</span><br><span style="color: hsl(0, 100%, 40%);">- target; 0: Disabled; <b>1: Enabled </b>.</span><br><span style="color: hsl(120, 100%, 40%);">+ target; <b>0: Disabled</b>; 1: Enabled.</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 TccOffsetLock;</span><br><span>@@ -2886,13 +2894,13 @@</span><br><span> </span><br><span> /** Offset 0x0870 - Package PL4 power limit</span><br><span> Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 1023875 in Step size of 125</span><br><span> **/</span><br><span> UINT32 PowerLimit4;</span><br><span> </span><br><span> /** Offset 0x0874 - Tcc Offset Time Window for RATL</span><br><span> Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid</span><br><span style="color: hsl(0, 100%, 40%);">- Range 0 to 4095875 in Step size of 125</span><br><span style="color: hsl(120, 100%, 40%);">+ Range 0 to 1023875 in Step size of 125</span><br><span> **/</span><br><span> UINT32 TccOffsetTimeWindowForRatl;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25289">change 25289</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 </div>
<div style="display:none"> Gerrit-Change-Number: 25289 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>