[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Modified memory dimm settings

Kin Wai Ng (Code Review) gerrit at coreboot.org
Fri Mar 16 14:31:05 CET 2018


Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/25230

to review the following change.


Change subject: mainboard/intel/coffeelake_rvp: Modified memory dimm settings
......................................................................

mainboard/intel/coffeelake_rvp: Modified memory dimm settings

Change-Id: I9bf2897fcafe63bfe32678a4d49d88b08f5d35bf
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
M src/mainboard/intel/coffeelake_rvp/romstage.c
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
2 files changed, 7 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/25230/1

diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c
index a2c719b..eba02ef 100755
--- a/src/mainboard/intel/coffeelake_rvp/romstage.c
+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c
@@ -39,6 +39,12 @@
 	mem_cfg->DqPinsInterleaved = 1;
 	mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */
 	mem_cfg->ECT = 1; /* Early Command Training Enabled */
+	mem_cfg->SafeMode = 0;
+	mem_cfg->RaplLim1WindX = 0;
+	mem_cfg->RaplLim1WindY = 0;
+	mem_cfg->RaplLim1Pwr = 0;
+	mem_cfg->RhPrevention = 1;
+
 	spd_index = 2;
 
 	struct region_device spd_rdev;
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index 3867ff9..0a18432 100755
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -6,6 +6,7 @@
 
 	# FSP configuration
 	register "SaGv" = "3"
+	register "RMT" = "1"
 	register "FspSkipMpInit" = "0"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9bf2897fcafe63bfe32678a4d49d88b08f5d35bf
Gerrit-Change-Number: 25230
Gerrit-PatchSet: 1
Gerrit-Owner: Kin Wai Ng <kin.wai.ng at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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