[coreboot-gerrit] Change in coreboot[master]: soc/intel/coffeelake: Include Coffeelake Device Ids
Kin Wai Ng (Code Review)
gerrit at coreboot.org
Fri Mar 16 14:31:01 CET 2018
Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/25224
to review the following change.
Change subject: soc/intel/coffeelake: Include Coffeelake Device Ids
......................................................................
soc/intel/coffeelake: Include Coffeelake Device Ids
Add Coffeelake specific CPU, System Agent, PCH, IGD Device ID, etc.
Change-Id: Ia8417199205c26b9147f7b04a2418ca22ffc188b
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/coffeelake/bootblock/report_platform.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
18 files changed, 82 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25224/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
old mode 100644
new mode 100755
index c184383..cd534f9
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2682,6 +2682,8 @@
#define PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC 0x9d85
#define PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC 0x9d84
#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370 0xa306
+#define PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370 0xa30c
/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
@@ -2760,6 +2762,23 @@
#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15 0x9db6
#define PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16 0x9db7
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1 0xa338
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2 0xa339
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3 0xa33a
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4 0xa33b
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5 0xa33c
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6 0xa33d
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7 0xa33e
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8 0xa33f
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9 0xa330
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10 0xa331
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11 0xa332
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12 0xa333
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13 0xa334
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14 0xa335
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15 0xa336
+#define PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16 0xa337
+
/* Intel SATA device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03
#define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07
@@ -2769,6 +2788,7 @@
#define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5
#define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7
#define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a
+#define PCI_DEVICE_ID_INTEL_CNL_H_SATA 0xa352
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
@@ -2777,6 +2797,7 @@
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
+#define PCI_DEVICE_ID_INTEL_CNL_H_PMC 0xa321
/* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
@@ -2811,6 +2832,10 @@
#define PCI_DEVICE_ID_INTEL_CNL_I2C3 0x9deb
#define PCI_DEVICE_ID_INTEL_CNL_I2C4 0x9dc5
#define PCI_DEVICE_ID_INTEL_CNL_I2C5 0x9dc6
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C0 0xa368
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C1 0xa369
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C2 0xa36a
+#define PCI_DEVICE_ID_INTEL_CNL_H_I2C3 0xa36b
/* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
@@ -2833,6 +2858,9 @@
#define PCI_DEVICE_ID_INTEL_CNL_UART0 0x9da8
#define PCI_DEVICE_ID_INTEL_CNL_UART1 0x9da9
#define PCI_DEVICE_ID_INTEL_CNL_UART2 0x9dc7
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART0 0xa328
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART1 0xa329
+#define PCI_DEVICE_ID_INTEL_CNL_H_UART2 0xa347
/* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
@@ -2875,6 +2903,7 @@
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42
#define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A
+#define PCI_DEVICE_ID_INTEL_CFL_H 0x3e9b
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@@ -2891,12 +2920,14 @@
#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f
#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
+#define PCI_DEVICE_ID_INTEL_CNL_ID_H 0x3ec4
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
#define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3
#define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3
+#define PCI_DEVICE_ID_INTEL_CNL_H_SMBUS 0xa323
/* Intel XHCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
@@ -2905,16 +2936,19 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af
#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
+#define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d
/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
#define PCI_DEVICE_ID_INTEL_GLK_P2SB 0x3192
#define PCI_DEVICE_ID_INTEL_CNL_P2SB 0x9da0
+#define PCI_DEVICE_ID_INTEL_CNL_H_P2SB 0xa320
/* Intel SRAM device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec
#define PCI_DEVICE_ID_INTEL_GLK_SRAM 0x31ec
#define PCI_DEVICE_ID_INTEL_CNL_SRAM 0x9def
+#define PCI_DEVICE_ID_INTEL_CNL_H_SRAM 0xa36f
/* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
@@ -2922,24 +2956,28 @@
#define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8
#define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70
#define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71
+#define PCI_DEVICE_ID_INTEL_CNL_H_AUDIO 0xa348
/* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
#define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a
#define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0
#define PCI_DEVICE_ID_INTEL_SKL_CSE0 0x9d3a
+#define PCI_DEVICE_ID_INTEL_CNL_H_CSE0 0xa360
/* Intel XDCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa
#define PCI_DEVICE_ID_INTEL_GLK_XDCI 0x31aa
#define PCI_DEVICE_ID_INTEL_SPT_LP_XDCI 0x9d30
#define PCI_DEVICE_ID_INTEL_CNL_LP_XDCI 0x9dee
+#define PCI_DEVICE_ID_INTEL_CNL_H_XDCI 0xa36e
/* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
#define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d
#define PCI_DEVICE_ID_INTEL_CNL_SD 0x9df5
+#define PCI_DEVICE_ID_INTEL_CNL_H_SD 0xa375
/* Intel EMMC device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b
@@ -2952,6 +2990,8 @@
#define PCH_CNL_LP_U_PREMIUM 0x9d84
#define PCH_CNL_LP_U_BASE 0x9d85
#define PCH_CNL_H_DT_SUPER 0xa280
+#define PCH_CNL_H_MOBILE_Q370 0xa306
+#define PCH_CNL_H_MOBILE_QM370 0xa30c
#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
diff --git a/src/soc/intel/coffeelake/bootblock/report_platform.c b/src/soc/intel/coffeelake/bootblock/report_platform.c
old mode 100644
new mode 100755
index c37f475..4748004
--- a/src/soc/intel/coffeelake/bootblock/report_platform.c
+++ b/src/soc/intel/coffeelake/bootblock/report_platform.c
@@ -32,41 +32,29 @@
u32 cpuid;
const char *name;
} cpu_table[] = {
- { CPUID_CANNONLAKE_A0, "Cannonlake A0" },
- { CPUID_CANNONLAKE_B0, "Cannonlake B0" },
- { CPUID_CANNONLAKE_C0, "Cannonlake C0" },
- { CPUID_CANNONLAKE_D0, "Cannonlake D0" },
+ { CPUID_COFFEELAKE_A0, "Coffeelake A0" },
};
static struct {
u16 mchid;
const char *name;
} mch_table[] = {
- { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
- { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
+ { PCI_DEVICE_ID_INTEL_CNL_ID_H, "CoffeeLake Halo (6+2)" },
};
static struct {
u16 lpcid;
const char *name;
} pch_table[] = {
- { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
- { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
- { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370, "Coffeelake-H" },
+ { PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370, "Coffeelake-H" },
};
static struct {
u16 igdid;
const char *name;
} igd_table[] = {
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
- { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
+ { PCI_DEVICE_ID_INTEL_CFL_H, "Coffeelake H" },
};
static uint8_t get_dev_revision(device_t dev)
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
old mode 100644
new mode 100755
index 085a340..40086e4
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -69,6 +69,7 @@
{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 },
{ X86_VENDOR_INTEL, CPUID_GLK_A0 },
{ X86_VENDOR_INTEL, CPUID_GLK_B0 },
+ { X86_VENDOR_INTEL, CPUID_COFFEELAKE_A0 },
{ 0, 0 },
};
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
old mode 100644
new mode 100755
index 4991db6..d57cb7f
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -514,6 +514,7 @@
PCI_DEVICE_ID_INTEL_GLK_CSE0,
PCI_DEVICE_ID_INTEL_CNL_CSE0,
PCI_DEVICE_ID_INTEL_SKL_CSE0,
+ PCI_DEVICE_ID_INTEL_CNL_H_CSE0,
0,
};
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
old mode 100644
new mode 100755
index 365fab7..2b11cd8
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -31,6 +31,7 @@
PCI_DEVICE_ID_INTEL_CNL_AUDIO,
PCI_DEVICE_ID_INTEL_GLK_AUDIO,
PCI_DEVICE_ID_INTEL_SKL_AUDIO,
+ PCI_DEVICE_ID_INTEL_CNL_H_AUDIO,
0,
};
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
old mode 100644
new mode 100755
index dcf8200..fa63477
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -128,6 +128,7 @@
PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
+ PCI_DEVICE_ID_INTEL_CFL_H,
0,
};
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
old mode 100644
new mode 100755
index 7dd40db..95b5bae
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -93,6 +93,10 @@
PCI_DEVICE_ID_INTEL_GLK_I2C5,
PCI_DEVICE_ID_INTEL_GLK_I2C6,
PCI_DEVICE_ID_INTEL_GLK_I2C7,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C0,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C1,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C2,
+ PCI_DEVICE_ID_INTEL_CNL_H_I2C3,
0,
};
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h
old mode 100644
new mode 100755
index 3057209..d9336b9
--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h
+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h
@@ -37,6 +37,7 @@
#define CPUID_APOLLOLAKE_E0 0x506ca
#define CPUID_GLK_A0 0x706a0
#define CPUID_GLK_B0 0x706a1
+#define CPUID_COFFEELAKE_A0 0x906ea
/*
* MP Init callback function to Find CPU Topology. This function is common
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
old mode 100644
new mode 100755
index 2efdc8d..b525ef8
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -140,6 +140,8 @@
PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_Q370,
+ PCI_DEVICE_ID_INTEL_CNL_H_LPC_QM370,
0
};
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
old mode 100644
new mode 100755
index 6a9bd34..23e279e
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -71,6 +71,7 @@
PCI_DEVICE_ID_INTEL_APL_P2SB,
PCI_DEVICE_ID_INTEL_GLK_P2SB,
PCI_DEVICE_ID_INTEL_CNL_P2SB,
+ PCI_DEVICE_ID_INTEL_CNL_H_P2SB,
0,
};
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
old mode 100644
new mode 100755
index 7d383fd..74f21e6
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -165,6 +165,22 @@
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP13,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP14,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP15,
+ PCI_DEVICE_ID_INTEL_CNL_H_PCIE_RP16,
0
};
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
old mode 100644
new mode 100755
index cabe895..b3e0672
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -76,6 +76,7 @@
PCI_DEVICE_ID_INTEL_CNL_SATA,
PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA,
PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA,
+ PCI_DEVICE_ID_INTEL_CNL_H_SATA,
0
};
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
old mode 100644
new mode 100755
index 66eaddf5..7d2bfb0
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -69,6 +69,7 @@
PCI_DEVICE_ID_INTEL_CNL_SD,
PCI_DEVICE_ID_INTEL_GLK_SD,
PCI_DEVICE_ID_INTEL_SKL_SD,
+ PCI_DEVICE_ID_INTEL_CNL_H_SD,
0
};
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
old mode 100644
new mode 100755
index 3793025..f27a53b
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -91,7 +91,7 @@
PCI_DEVICE_ID_INTEL_CNL_SMBUS,
PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS,
PCI_DEVICE_ID_INTEL_SPT_H_SMBUS,
- PCI_DEVICE_ID_INTEL_KBP_H_SMBUS,
+ PCI_DEVICE_ID_INTEL_CNL_H_SMBUS,
0
};
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
old mode 100644
new mode 100755
index 027222b..4be9cae
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -299,6 +299,7 @@
PCI_DEVICE_ID_INTEL_KBL_ID_H,
PCI_DEVICE_ID_INTEL_KBL_U_R,
PCI_DEVICE_ID_INTEL_KBL_ID_DT,
+ PCI_DEVICE_ID_INTEL_CNL_ID_H,
0
};
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
old mode 100644
new mode 100755
index 9f26ef1..582d5cf
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -168,6 +168,9 @@
PCI_DEVICE_ID_INTEL_GLK_UART1,
PCI_DEVICE_ID_INTEL_GLK_UART2,
PCI_DEVICE_ID_INTEL_GLK_UART3,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART0,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART1,
+ PCI_DEVICE_ID_INTEL_CNL_H_UART2,
0,
};
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
old mode 100644
new mode 100755
index 10e6f0d..6a61d5e
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -35,6 +35,7 @@
PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,
PCI_DEVICE_ID_INTEL_GLK_XDCI,
PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+ PCI_DEVICE_ID_INTEL_CNL_H_XDCI,
0
};
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
old mode 100644
new mode 100755
index e5a4f9b..dd11e83
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -37,6 +37,7 @@
PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
+ PCI_DEVICE_ID_INTEL_CNP_H_XHCI,
0
};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia8417199205c26b9147f7b04a2418ca22ffc188b
Gerrit-Change-Number: 25224
Gerrit-PatchSet: 1
Gerrit-Owner: Kin Wai Ng <kin.wai.ng at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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