[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/coffeelake: Add support for FSP tempraminit for CFL
Kin Wai Ng (Code Review)
gerrit at coreboot.org
Fri Mar 16 14:31:02 CET 2018
Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/25225
to review the following change.
Change subject: src/soc/intel/coffeelake: Add support for FSP tempraminit for CFL
......................................................................
src/soc/intel/coffeelake: Add support for FSP tempraminit for CFL
Coreboot will used FSP tempraminit binary, fspt.bin, to initialize the
Cache-As-Ram and also to update the soc microcode.
Thus, no longer using native Coreboot implementation of Cache-As-Ram.
Change-Id: I9bec27b5cd358a470be694459f8e347e9ce6ac8e
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
M src/mainboard/intel/coffeelake_rvp/Kconfig
M src/soc/intel/coffeelake/Makefile.inc
A src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S
A src/soc/intel/coffeelake/exit_car_fsp.S
4 files changed, 154 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25225/1
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
old mode 100644
new mode 100755
index df7c5ae..47cc7a3
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -9,7 +9,6 @@
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
select DRIVERS_I2C_HID
select DRIVERS_I2C_GENERIC
diff --git a/src/soc/intel/coffeelake/Makefile.inc b/src/soc/intel/coffeelake/Makefile.inc
old mode 100644
new mode 100755
index 803414d..be201b4
--- a/src/soc/intel/coffeelake/Makefile.inc
+++ b/src/soc/intel/coffeelake/Makefile.inc
@@ -20,6 +20,7 @@
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
+bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_FSP.S
romstage-$(CONFIG_SOC_INTEL_COFFEELAKE_LPDDR4_INIT) += cfl_lpddr4_init.c
romstage-y += gpio.c
@@ -62,6 +63,7 @@
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
+postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
verstage-y += gspi.c
verstage-y += i2c.c
diff --git a/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S
new file mode 100755
index 0000000..4b17129
--- /dev/null
+++ b/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
+
+#include <../../../arch/x86/walkcbfs.S>
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+.global cache_as_ram
+cache_as_ram:
+ post_code(0x21)
+
+ /* find fsp in cbfs */
+ lea fsp_name, %esi
+ mov $1f, %esp
+ jmp walkcbfs_asm
+
+1:
+ cmp $0, %eax
+ jz .halt_forever
+ mov CBFS_FILE_OFFSET(%eax), %ebx
+ bswap %ebx
+ add %eax, %ebx
+ add $0x94, %ebx
+
+ /*
+ * ebx = FSP INFO HEADER
+ * Calculate entry into FSP
+ */
+ mov 0x30(%ebx), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebx), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+
+ /* Setup bootblock stack */
+ mov %edx, %esp
+
+ /* clear CAR_GLOBAL area as it is not shared */
+ cld
+ xor %eax, %eax
+ movl $(_car_global_end), %ecx
+ movl $(_car_global_start), %edi
+ sub %edi, %ecx
+ rep stosl
+ nop
+
+ /* We can call into C functions now */
+ call bootblock_c_entry
+
+ /* Never reached */
+
+.halt_forever:
+ post_code(POST_DEAD_CODE)
+ hlt
+ jmp .halt_forever
+
+CAR_init_params:
+ .long 0x545F4450 /*CFLUPD_T*/
+ .long 0x554C4643
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
+
+
+fsp_name:
+ .ascii "fspt.bin\x00"
diff --git a/src/soc/intel/coffeelake/exit_car_fsp.S b/src/soc/intel/coffeelake/exit_car_fsp.S
new file mode 100755
index 0000000..e7457e0
--- /dev/null
+++ b/src/soc/intel/coffeelake/exit_car_fsp.S
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call. More info can be found in the Apollo Lake FSP
+ * Integration Guide included with the FSP binary. The below
+ * caching settings are based on an 8MiB Flash Size given as a
+ * parameter to TempRamInit.
+ *
+ * TempRamExit MTRR Settings:
+ * 0x00000000 - 0x0009FFFF | Write Back
+ * 0x000C0000 - Top of Low Memory | Write Back
+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
+ * 0x100000000 - Top of High Memory | Write Back
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+ /* Set up new stack. */
+ mov post_car_stack_top, %esp
+
+ /* Call C code */
+ call main
--
To view, visit https://review.coreboot.org/25225
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9bec27b5cd358a470be694459f8e347e9ce6ac8e
Gerrit-Change-Number: 25225
Gerrit-PatchSet: 1
Gerrit-Owner: Kin Wai Ng <kin.wai.ng at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela at intel.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180316/4b0e0784/attachment-0001.html>
More information about the coreboot-gerrit
mailing list