<p>Kin Wai Ng would like Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela and Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25225">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/intel/coffeelake: Add support for FSP tempraminit for CFL<br><br>Coreboot will used FSP tempraminit binary, fspt.bin, to initialize the<br>Cache-As-Ram and also to update the soc microcode.<br><br>Thus, no longer using native Coreboot implementation of Cache-As-Ram.<br><br>Change-Id: I9bec27b5cd358a470be694459f8e347e9ce6ac8e<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/Kconfig<br>M src/soc/intel/coffeelake/Makefile.inc<br>A src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S<br>A src/soc/intel/coffeelake/exit_car_fsp.S<br>4 files changed, 154 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25225/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index df7c5ae..47cc7a3</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig</span><br><span>@@ -9,7 +9,6 @@</span><br><span> select GENERIC_SPD_BIN</span><br><span> select HAVE_ACPI_RESUME</span><br><span> select HAVE_ACPI_TABLES</span><br><span style="color: hsl(0, 100%, 40%);">- select MAINBOARD_HAS_CHROMEOS</span><br><span> select GENERIC_SPD_BIN</span><br><span> select DRIVERS_I2C_HID</span><br><span> select DRIVERS_I2C_GENERIC</span><br><span>diff --git a/src/soc/intel/coffeelake/Makefile.inc b/src/soc/intel/coffeelake/Makefile.inc</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 803414d..be201b4</span><br><span>--- a/src/soc/intel/coffeelake/Makefile.inc</span><br><span>+++ b/src/soc/intel/coffeelake/Makefile.inc</span><br><span>@@ -20,6 +20,7 @@</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_FSP.S</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_COFFEELAKE_LPDDR4_INIT) += cfl_lpddr4_init.c</span><br><span> romstage-y += gpio.c</span><br><span>@@ -62,6 +63,7 @@</span><br><span> postcar-y += memmap.c</span><br><span> postcar-y += pmutil.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S</span><br><span> </span><br><span> verstage-y += gspi.c</span><br><span> verstage-y += i2c.c</span><br><span>diff --git a/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S</span><br><span>new file mode 100755</span><br><span>index 0000000..4b17129</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/coffeelake/bootblock/cache_as_ram_FSP.S</span><br><span>@@ -0,0 +1,106 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <../../../arch/x86/walkcbfs.S></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global bootblock_pre_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock_pre_c_entry:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global cache_as_ram</span><br><span style="color: hsl(120, 100%, 40%);">+cache_as_ram:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x21)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* find fsp in cbfs */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea fsp_name, %esi</span><br><span style="color: hsl(120, 100%, 40%);">+ mov $1f, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp walkcbfs_asm</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+1:</span><br><span style="color: hsl(120, 100%, 40%);">+ cmp $0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ jz .halt_forever</span><br><span style="color: hsl(120, 100%, 40%);">+ mov CBFS_FILE_OFFSET(%eax), %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ bswap %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ add %eax, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ add $0x94, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ebx = FSP INFO HEADER</span><br><span style="color: hsl(120, 100%, 40%);">+ * Calculate entry into FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov 0x30(%ebx), %eax /* Load TempRamInitEntry */</span><br><span style="color: hsl(120, 100%, 40%);">+ add 0x1c(%ebx), %eax /* add in the offset for FSP */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pass early init variables on a fake stack (no memory yet)</span><br><span style="color: hsl(120, 100%, 40%);">+ * as well as the return location</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ lea CAR_init_stack, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* call FSP binary to setup temporary stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%eax</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_done:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup bootblock stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %edx, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* clear CAR_GLOBAL area as it is not shared */</span><br><span style="color: hsl(120, 100%, 40%);">+ cld</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_end), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_start), %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ sub %edi, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span style="color: hsl(120, 100%, 40%);">+ nop</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We can call into C functions now */</span><br><span style="color: hsl(120, 100%, 40%);">+ call bootblock_c_entry</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Never reached */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.halt_forever:</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(120, 100%, 40%);">+ hlt</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp .halt_forever</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_params:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x545F4450 /*CFLUPD_T*/</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x554C4643</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CONFIG_ROM_SIZE /* Total Firmware Length */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CAR_init_stack:</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_done</span><br><span style="color: hsl(120, 100%, 40%);">+ .long CAR_init_params</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+fsp_name:</span><br><span style="color: hsl(120, 100%, 40%);">+ .ascii "fspt.bin\x00"</span><br><span>diff --git a/src/soc/intel/coffeelake/exit_car_fsp.S b/src/soc/intel/coffeelake/exit_car_fsp.S</span><br><span>new file mode 100755</span><br><span>index 0000000..e7457e0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/coffeelake/exit_car_fsp.S</span><br><span>@@ -0,0 +1,46 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cr.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.</span><br><span style="color: hsl(120, 100%, 40%);">+ * This version of chipset_teardown_car sets up the stack, then bypasses</span><br><span style="color: hsl(120, 100%, 40%);">+ * the rest of arch/x86/exit_car.S and calls main() itself instead of</span><br><span style="color: hsl(120, 100%, 40%);">+ * returning to _start. In main(), the TempRamExit FSP API is called</span><br><span style="color: hsl(120, 100%, 40%);">+ * to tear down the CAR and set up caching which can be overwritten</span><br><span style="color: hsl(120, 100%, 40%);">+ * after the API call. More info can be found in the Apollo Lake FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ * Integration Guide included with the FSP binary. The below</span><br><span style="color: hsl(120, 100%, 40%);">+ * caching settings are based on an 8MiB Flash Size given as a</span><br><span style="color: hsl(120, 100%, 40%);">+ * parameter to TempRamInit.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * TempRamExit MTRR Settings:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.text</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set up new stack. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov post_car_stack_top, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Call C code */</span><br><span style="color: hsl(120, 100%, 40%);">+ call main</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25225">change 25225</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25225"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9bec27b5cd358a470be694459f8e347e9ce6ac8e </div>
<div style="display:none"> Gerrit-Change-Number: 25225 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>