[coreboot-gerrit] Change in coreboot[master]: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
Kin Wai Ng (Code Review)
gerrit at coreboot.org
Fri Mar 16 10:30:32 CET 2018
Kin Wai Ng has uploaded this change for review. ( https://review.coreboot.org/25219
Change subject: fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
......................................................................
fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34
Header files based on FSP 7.0.25.34
Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37
Signed-off-by: Ng Kin Wai <kin.wai.ng at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
5 files changed, 461 insertions(+), 454 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/25219/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
index 0dbafff..fca01e9 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
@@ -1,67 +1,67 @@
-/** @file
- Header file for Firmware Version Information
-
- Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
- UINT8 Count; ///< Offset 28 Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
+/** @file
+ Header file for Firmware Version Information
+
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+ UINT8 MajorVersion;
+ UINT8 MinorVersion;
+ UINT8 Revision;
+ UINT16 BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
index feb2022..ae25814 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
@@ -37,11 +37,11 @@
#pragma pack(1)
-#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */
+#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */
-#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */
+#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */
#pragma pack()
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
index d014f81..a147f4f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
@@ -37,19 +37,19 @@
#pragma pack(1)
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
/** Fsp M Configuration
**/
@@ -182,9 +182,15 @@
**/
UINT8 ProbelessTrace;
-/** Offset 0x00A3
+/** Offset 0x00A3 - GDXC IOT SIZE
+ Size of IOT and MOT is in 8 MB chunks
**/
- UINT8 UnusedUpdSpace0[2];
+ UINT8 GdxcIotSize;
+
+/** Offset 0x00A4 - GDXC MOT SIZE
+ Size of IOT and MOT is in 8 MB chunks
+**/
+ UINT8 GdxcMotSize;
/** Offset 0x00A5 - Enable SMBus
Enable/disable SMBus controller.
@@ -244,9 +250,7 @@
/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
Size of memory preallocated for internal graphics.
- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB,
- 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,
- 0xFD:56MB, 0xFE:60MB
+ 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
**/
UINT8 IgdDvmt50PreAlloc;
@@ -272,14 +276,14 @@
/** Offset 0x00BC - SA GV
System Agent dynamic frequency support and when enabled memory will be training
at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
- 2=FixedMid, 3=FixedHigh, and 4=Enabled.
- 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
+ 2=FixedHigh, and 3=Enabled.
+ 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
**/
UINT8 SaGv;
/** Offset 0x00BD
**/
- UINT8 UnusedUpdSpace1;
+ UINT8 UnusedUpdSpace0;
/** Offset 0x00BE - DDR Frequency Limit
Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
@@ -329,7 +333,7 @@
/** Offset 0x00C8
**/
- UINT8 UnusedUpdSpace2[16];
+ UINT8 UnusedUpdSpace1[16];
/** Offset 0x00D8 - SPD Profile Selected
Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
@@ -488,7 +492,7 @@
/** Offset 0x00F8
**/
- UINT8 UnusedUpdSpace3[4];
+ UINT8 UnusedUpdSpace2[4];
/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
@@ -510,7 +514,7 @@
/** Offset 0x00FF
**/
- UINT8 UnusedUpdSpace4;
+ UINT8 UnusedUpdSpace3;
/** Offset 0x0100 - HECI1 BAR address
BAR address of HECI1
@@ -681,7 +685,7 @@
/** Offset 0x0125
**/
- UINT8 UnusedUpdSpace5[3];
+ UINT8 UnusedUpdSpace4[3];
/** Offset 0x0128 - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@@ -720,7 +724,7 @@
/** Offset 0x0146
**/
- UINT8 UnusedUpdSpace6[2];
+ UINT8 UnusedUpdSpace5[2];
/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
@@ -957,7 +961,7 @@
/** Offset 0x0207
**/
- UINT8 UnusedUpdSpace7;
+ UINT8 UnusedUpdSpace6;
/** Offset 0x0208 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
@@ -1112,7 +1116,7 @@
/** Offset 0x0227
**/
- UINT8 UnusedUpdSpace8;
+ UINT8 UnusedUpdSpace7;
/** Offset 0x0228 - PrmrrSize
0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
@@ -2275,25 +2279,16 @@
**/
UINT8 EnBER;
-/** Offset 0x050F - PEG IMR support
- This option configures the IMR support for PEG.(def=Disable)
- $EN_DIS
+/** Offset 0x050F - Dual Dimm Per-Channel Board Type
+ Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
+ to limit maximum frequency for some SKUs.
+ 0:1DPC, 1:2DPC
**/
- UINT8 PegImrEnable;
+ UINT8 DualDimmPerChannelBoardType;
-/** Offset 0x0510 - PEG IMR size
- The size of IMR to be allocated for PEG EndPoint device
+/** Offset 0x0510
**/
- UINT16 PegImrSize;
-
-/** Offset 0x0512 - PEG Root Port Selection
- The Root Port for which the IMR to be allocated
-**/
- UINT8 PegImrRpSelection;
-
-/** Offset 0x0513
-**/
- UINT8 ReservedFspmUpd[12];
+ UINT8 ReservedFspmUpd[15];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
@@ -2518,7 +2513,7 @@
/** Offset 0x0579
**/
- UINT8 UnusedUpdSpace10;
+ UINT8 UnusedUpdSpace9;
/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
Range: 0-65535, default is 1000. @warning Do not change from the default
@@ -2793,7 +2788,7 @@
/** Offset 0x051F
**/
- UINT8 UnusedUpdSpace9;
+ UINT8 UnusedUpdSpace8;
/** Offset 0x0520
**/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
index 0f3577a..5725dd3 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
@@ -37,49 +37,49 @@
#pragma pack(1)
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
/** Fsp S Configuration
**/
@@ -717,8 +717,8 @@
UINT8 PavpEnable;
/** Offset 0x0217 - CdClock Frequency selection
- 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz
- 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz
+ 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz
+ 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz
**/
UINT8 CdClock;
@@ -2335,7 +2335,7 @@
UINT8 PmSupport;
/** Offset 0x07BC - Enable/Disable CdynmaxClamp
- Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
$EN_DIS
**/
UINT8 CdynmaxClampEnable;
@@ -2784,8 +2784,8 @@
UINT8 CstateLatencyControl5TimeUnit;
/** Offset 0x0819 - Interrupt Redirection Mode Select
- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
- No change.
+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
**/
UINT8 PpmIrmSetting;
@@ -3032,11 +3032,23 @@
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x08A5 - ReservedCpuPostMemTest
+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C3StateAutoDemotion;
+
+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C3StateUnDemotion;
+
+/** Offset 0x08A7 - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
- UINT8 ReservedCpuPostMemTest[21];
+ UINT8 ReservedCpuPostMemTest[19];
/** Offset 0x08BA - SgxSinitDataFromTpm
SgxSinitDataFromTpm default values
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
index 941a891..e2a3e09 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
@@ -1,288 +1,288 @@
-/** @file
- This file contains definitions required for creation of
- Memory S3 Save data, Memory Info data and Memory Platform
- data hobs.
-
- at copyright
- INTEL CONFIDENTIAL
- Copyright 1999 - 2018 Intel Corporation.
-
- The source code contained or described herein and all documents related to the
- source code ("Material") are owned by Intel Corporation or its suppliers or
- licensors. Title to the Material remains with Intel Corporation or its suppliers
- and licensors. The Material may contain trade secrets and proprietary and
- confidential information of Intel Corporation and its suppliers and licensors,
- and is protected by worldwide copyright and trade secret laws and treaty
- provisions. No part of the Material may be used, copied, reproduced, modified,
- published, uploaded, posted, transmitted, distributed, or disclosed in any way
- without Intel's prior express written permission.
-
- No license under any patent, copyright, trade secret or other intellectual
- property right is granted to or conferred upon you by disclosure or delivery
- of the Materials, either expressly, by implication, inducement, estoppel or
- otherwise. Any license under such intellectual property rights must be
- express and approved by Intel in writing.
-
- Unless otherwise agreed by Intel in writing, you may not remove or alter
- this notice or any other notice embedded in Materials by Intel or
- Intel's suppliers or licensors in any way.
-
- This file contains an 'Intel Peripheral Driver' and is uniquely identified as
- "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
- the terms of your license agreement with Intel or your vendor. This file may
- be modified by the user, subject to additional terms of the license agreement.
-
- at par Specification Reference:
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_NODE 1
-#define MAX_CH 2
-#define MAX_DIMM 2
-
-///
-/// Host reset states from MRC.
-///
-#define WARM_BOOT 2
-
-#define R_MC_CHNL_RANK_PRESENT 0x7C
-#define B_RANK0_PRS BIT0
-#define B_RANK1_PRS BIT1
-#define B_RANK2_PRS BIT4
-#define B_RANK3_PRS BIT5
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
- UINT8 Major; ///< Major version number
- UINT8 Minor; ///< Minor version number
- UINT8 Rev; ///< Revision number
- UINT8 Build; ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcChannelSts enum in MRC
-//
-#ifndef CHANNEL_NOT_PRESENT
-#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
-#endif
-#ifndef CHANNEL_DISABLED
-#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
-#endif
-#ifndef CHANNEL_PRESENT
-#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
-#endif
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef bmCold
-#define bmCold 0 // Cold boot
-#endif
-#ifndef bmWarm
-#define bmWarm 1 // Warm boot
-#endif
-#ifndef bmS3
-#define bmS3 2 // S3 resume
-#endif
-#ifndef bmFast
-#define bmFast 3 // Fast boot
-#endif
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
-#endif
-#ifndef CPU_CFL//CNL
-#ifndef MRC_DDR_TYPE_LPDDR4
-#define MRC_DDR_TYPE_LPDDR4 3
-#endif
-#else//CFL
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 3
-#endif
-#endif//CPU_CFL-endif
-
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
- UINT32 tCK; ///< Memory cycle time, in femtoseconds.
- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-typedef struct {
- UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
- UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
- UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
- UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
-} MRC_TA_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
-} CONTROLLER_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT16 DataWidth; ///< Data width, in bits, of this memory device
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
-
- SiMrcVersion Version;
- BOOLEAN EccSupport;
- UINT8 MemoryProfile;
- UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
- UINT8 Ratio;
- UINT8 RefClk;
- UINT32 VddVoltage[MAX_PROFILE_NUM];
- CONTROLLER_INFO Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
- Memory Platform Data Hob
-
- <b>Revision 1:</b>
- - Initial version.
- <b>Revision 2:</b>
- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 BootMode;
- UINT32 TsegSize;
- UINT32 TsegBase;
- UINT32 PrmrrSize;
- UINT32 PrmrrBase;
- UINT32 GttBase;
- UINT32 MmioSize;
- UINT32 PciEBaseAddress;
-#ifdef CPU_CFL
- UINT32 GdxcIotBase;
- UINT32 GdxcIotSize;
- UINT32 GdxcMotBase;
- UINT32 GdxcMotSize;
-#endif //CPU_CFL
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
- MEMORY_PLATFORM_DATA Data;
- UINT8 *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+ at copyright
+ INTEL CONFIDENTIAL
+ Copyright 1999 - 2018 Intel Corporation.
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
+
+ at par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef bmCold
+#define bmCold 0 // Cold boot
+#endif
+#ifndef bmWarm
+#define bmWarm 1 // Warm boot
+#endif
+#ifndef bmS3
+#define bmS3 2 // S3 resume
+#endif
+#ifndef bmFast
+#define bmFast 3 // Fast boot
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef CPU_CFL//CNL
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#else//CFL
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 3
+#endif
+#endif//CPU_CFL-endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+typedef struct {
+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
+} MRC_TA_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT32 PrmrrBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+#ifdef CPU_CFL
+ UINT32 GdxcIotBase;
+ UINT32 GdxcIotSize;
+ UINT32 GdxcMotBase;
+ UINT32 GdxcMotSize;
+#endif //CPU_CFL
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37
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