<p>Kin Wai Ng has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25219">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">fsp/fsp2_0/coffeelake: Add CFL FSP UPD Headers to ver 7.0.25.34<br><br>Header files based on FSP 7.0.25.34<br><br>Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h<br>5 files changed, 461 insertions(+), 454 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/25219/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h</span><br><span>index 0dbafff..fca01e9 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h</span><br><span>@@ -1,67 +1,67 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/** @file</span><br><span style="color: hsl(0, 100%, 40%);">- Header file for Firmware Version Information</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- This program and the accompanying materials are licensed and made available under</span><br><span style="color: hsl(0, 100%, 40%);">- the terms and conditions of the BSD License which accompanies this distribution.</span><br><span style="color: hsl(0, 100%, 40%);">- The full text of the license may be found at</span><br><span style="color: hsl(0, 100%, 40%);">- http://opensource.org/licenses/bsd-license.php</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,</span><br><span style="color: hsl(0, 100%, 40%);">- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <Uefi/UefiMultiPhase.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <Pi/PiBootMode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <Pi/PiHob.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack(1)</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Firmware Version Structure</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MajorVersion;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MinorVersion;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Revision;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 BuildNumber;</span><br><span style="color: hsl(0, 100%, 40%);">-} FIRMWARE_VERSION;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Firmware Version Information Structure</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String</span><br><span style="color: hsl(0, 100%, 40%);">- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version</span><br><span style="color: hsl(0, 100%, 40%);">-} FIRMWARE_VERSION_INFO;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef __SMBIOS_STANDARD_H__</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// The Smbios structure header.</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Type;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Length;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Handle;</span><br><span style="color: hsl(0, 100%, 40%);">-} SMBIOS_STRUCTURE;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Firmware Version Information HOB Structure</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB</span><br><span style="color: hsl(0, 100%, 40%);">- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Count; ///< Offset 28 Number of FVI elements included.</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-} FIRMWARE_VERSION_INFO_HOB;</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack()</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif // _FIRMWARE_VERSION_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file
</span><br><span style="color: hsl(120, 100%, 40%);">+ Header file for Firmware Version Information
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ This program and the accompanying materials are licensed and made available under
</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms and conditions of the BSD License which accompanies this distribution.
</span><br><span style="color: hsl(120, 100%, 40%);">+ The full text of the license may be found at
</span><br><span style="color: hsl(120, 100%, 40%);">+ http://opensource.org/licenses/bsd-license.php
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
</span><br><span style="color: hsl(120, 100%, 40%);">+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+#define _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack(1)
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MajorVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MinorVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BuildNumber;
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
</span><br><span style="color: hsl(120, 100%, 40%);">+ FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SMBIOS_STANDARD_H__
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The Smbios structure header.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Type;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Length;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Handle;
</span><br><span style="color: hsl(120, 100%, 40%);">+} SMBIOS_STRUCTURE;
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Firmware Version Information HOB Structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
</span><br><span style="color: hsl(120, 100%, 40%);">+ SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Count; ///< Offset 28 Number of FVI elements included.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+} FIRMWARE_VERSION_INFO_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack()
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h</span><br><span>index feb2022..ae25814 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h</span><br><span>@@ -37,11 +37,11 @@</span><br><span> </span><br><span> #pragma pack(1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FSPT_UPD_SIGNATURE 0x545F4450554C4E43 /* 'CNLUPD_T' */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4E43 /* 'CNLUPD_M' */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FSPS_UPD_SIGNATURE 0x535F4450554C4E43 /* 'CNLUPD_S' */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */</span><br><span> </span><br><span> #pragma pack()</span><br><span> </span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>index d014f81..a147f4f 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h</span><br><span>@@ -37,19 +37,19 @@</span><br><span> </span><br><span> #pragma pack(1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <MemInfoHob.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Revision; ///< Chipset Init Info Revision</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Rsvd[3]; ///< Reserved</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table</span><br><span style="color: hsl(0, 100%, 40%);">-} CHIPSET_INIT_INFO;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <MemInfoHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision; ///< Chipset Init Info Revision
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rsvd[3]; ///< Reserved
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
</span><br><span style="color: hsl(120, 100%, 40%);">+} CHIPSET_INIT_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span> </span><br><span> /** Fsp M Configuration</span><br><span> **/</span><br><span>@@ -182,9 +182,15 @@</span><br><span> **/</span><br><span> UINT8 ProbelessTrace;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x00A3</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A3 - GDXC IOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace0[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcIotSize;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x00A4 - GDXC MOT SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ Size of IOT and MOT is in 8 MB chunks</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 GdxcMotSize;</span><br><span> </span><br><span> /** Offset 0x00A5 - Enable SMBus</span><br><span> Enable/disable SMBus controller.</span><br><span>@@ -244,9 +250,7 @@</span><br><span> </span><br><span> /** Offset 0x00B8 - Internal Graphics Pre-allocated Memory</span><br><span> Size of memory preallocated for internal graphics.</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB,</span><br><span style="color: hsl(0, 100%, 40%);">- 0xFD:56MB, 0xFE:60MB</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00:0 MB, 0x01:32 MB, 0x02:64 MB</span><br><span> **/</span><br><span> UINT8 IgdDvmt50PreAlloc;</span><br><span> </span><br><span>@@ -272,14 +276,14 @@</span><br><span> /** Offset 0x00BC - SA GV</span><br><span> System Agent dynamic frequency support and when enabled memory will be training</span><br><span> at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,</span><br><span style="color: hsl(0, 100%, 40%);">- 2=FixedMid, 3=FixedHigh, and 4=Enabled.</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ 2=FixedHigh, and 3=Enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled</span><br><span> **/</span><br><span> UINT8 SaGv;</span><br><span> </span><br><span> /** Offset 0x00BD</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace0;</span><br><span> </span><br><span> /** Offset 0x00BE - DDR Frequency Limit</span><br><span> Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,</span><br><span>@@ -329,7 +333,7 @@</span><br><span> </span><br><span> /** Offset 0x00C8</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace2[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[16];</span><br><span> </span><br><span> /** Offset 0x00D8 - SPD Profile Selected</span><br><span> Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP</span><br><span>@@ -488,7 +492,7 @@</span><br><span> </span><br><span> /** Offset 0x00F8</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace3[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace2[4];</span><br><span> </span><br><span> /** Offset 0x00FC - Enable Intel HD Audio (Azalia)</span><br><span> 0: Disable, 1: Enable (Default) Azalia controller</span><br><span>@@ -510,7 +514,7 @@</span><br><span> </span><br><span> /** Offset 0x00FF</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace4;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace3;</span><br><span> </span><br><span> /** Offset 0x0100 - HECI1 BAR address</span><br><span> BAR address of HECI1</span><br><span>@@ -681,7 +685,7 @@</span><br><span> </span><br><span> /** Offset 0x0125</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace5[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace4[3];</span><br><span> </span><br><span> /** Offset 0x0128 - DMI Gen3 Root port preset values per lane</span><br><span> Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane</span><br><span>@@ -720,7 +724,7 @@</span><br><span> </span><br><span> /** Offset 0x0146</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace6[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace5[2];</span><br><span> </span><br><span> /** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control</span><br><span> Range: 0-15, 12 is default for each bundle, must be specified based upon platform design</span><br><span>@@ -957,7 +961,7 @@</span><br><span> </span><br><span> /** Offset 0x0207</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace6;</span><br><span> </span><br><span> /** Offset 0x0208 - Maximum clr turbo ratio override</span><br><span> Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the</span><br><span>@@ -1112,7 +1116,7 @@</span><br><span> </span><br><span> /** Offset 0x0227</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace8;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7;</span><br><span> </span><br><span> /** Offset 0x0228 - PrmrrSize</span><br><span> 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000</span><br><span>@@ -2275,25 +2279,16 @@</span><br><span> **/</span><br><span> UINT8 EnBER;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x050F - PEG IMR support</span><br><span style="color: hsl(0, 100%, 40%);">- This option configures the IMR support for PEG.(def=Disable)</span><br><span style="color: hsl(0, 100%, 40%);">- $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x050F - Dual Dimm Per-Channel Board Type</span><br><span style="color: hsl(120, 100%, 40%);">+ Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used</span><br><span style="color: hsl(120, 100%, 40%);">+ to limit maximum frequency for some SKUs.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0:1DPC, 1:2DPC</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegImrEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DualDimmPerChannelBoardType;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0510 - PEG IMR size</span><br><span style="color: hsl(0, 100%, 40%);">- The size of IMR to be allocated for PEG EndPoint device</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0510</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 PegImrSize;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0512 - PEG Root Port Selection</span><br><span style="color: hsl(0, 100%, 40%);">- The Root Port for which the IMR to be allocated</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 PegImrRpSelection;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0513</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmUpd[12];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[15];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span> /** Fsp M Test Configuration</span><br><span>@@ -2518,7 +2513,7 @@</span><br><span> </span><br><span> /** Offset 0x0579</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace10;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace9;</span><br><span> </span><br><span> /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization</span><br><span> Range: 0-65535, default is 1000. @warning Do not change from the default</span><br><span>@@ -2793,7 +2788,7 @@</span><br><span> </span><br><span> /** Offset 0x051F</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace9;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace8;</span><br><span> </span><br><span> /** Offset 0x0520</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>index 0f3577a..5725dd3 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h</span><br><span>@@ -37,49 +37,49 @@</span><br><span> </span><br><span> #pragma pack(1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Azalia Header structure</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 VendorId; ///< Codec Vendor ID</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DeviceId; ///< Codec Device ID</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.</span><br><span style="color: hsl(0, 100%, 40%);">-} AZALIA_HEADER;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Audio Azalia Verb Table structure</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- AZALIA_HEADER Header; ///< AZALIA PCH header</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header</span><br><span style="color: hsl(0, 100%, 40%);">-} AUDIO_AZALIA_VERB_TABLE;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Refer to the definition of PCH_INT_PIN</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef enum {</span><br><span style="color: hsl(0, 100%, 40%);">- SiPchNoInt, ///< No Interrupt Pin</span><br><span style="color: hsl(0, 100%, 40%);">- SiPchIntA,</span><br><span style="color: hsl(0, 100%, 40%);">- SiPchIntB,</span><br><span style="color: hsl(0, 100%, 40%);">- SiPchIntC,</span><br><span style="color: hsl(0, 100%, 40%);">- SiPchIntD</span><br><span style="color: hsl(0, 100%, 40%);">-} SI_PCH_INT_PIN;</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Device; ///< Device number</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Function; ///< Device function</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Irq; ///< IRQ to be set for device.</span><br><span style="color: hsl(0, 100%, 40%);">-} SI_PCH_DEVICE_INTERRUPT_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Azalia Header structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 VendorId; ///< Codec Vendor ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< Codec Device ID
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
</span><br><span style="color: hsl(120, 100%, 40%);">+} AZALIA_HEADER;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Audio Azalia Verb Table structure
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_HEADER Header; ///< AZALIA PCH header
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
</span><br><span style="color: hsl(120, 100%, 40%);">+} AUDIO_AZALIA_VERB_TABLE;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Refer to the definition of PCH_INT_PIN
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchNoInt, ///< No Interrupt Pin
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntA,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntB,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntC,
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiPchIntD
</span><br><span style="color: hsl(120, 100%, 40%);">+} SI_PCH_INT_PIN;
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Device; ///< Device number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Function; ///< Device function
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Irq; ///< IRQ to be set for device.
</span><br><span style="color: hsl(120, 100%, 40%);">+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span> </span><br><span> /** Fsp S Configuration</span><br><span> **/</span><br><span>@@ -717,8 +717,8 @@</span><br><span> UINT8 PavpEnable;</span><br><span> </span><br><span> /** Offset 0x0217 - CdClock Frequency selection</span><br><span style="color: hsl(0, 100%, 40%);">- 0=168 Mhz, 1=336 Mhz, 2(Default)=528 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=168 Mhz, 1=336 Mhz, 2=528 Mhz, 3(Default)=675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 168 Mhz, 1: 336 Mhz, 2: 528 Mhz, 3: 675 Mhz</span><br><span> **/</span><br><span> UINT8 CdClock;</span><br><span> </span><br><span>@@ -2335,7 +2335,7 @@</span><br><span> UINT8 PmSupport;</span><br><span> </span><br><span> /** Offset 0x07BC - Enable/Disable CdynmaxClamp</span><br><span style="color: hsl(0, 100%, 40%);">- Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 CdynmaxClampEnable;</span><br><span>@@ -2784,8 +2784,8 @@</span><br><span> UINT8 CstateLatencyControl5TimeUnit;</span><br><span> </span><br><span> /** Offset 0x0819 - Interrupt Redirection Mode Select</span><br><span style="color: hsl(0, 100%, 40%);">- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:</span><br><span style="color: hsl(0, 100%, 40%);">- No change.</span><br><span style="color: hsl(120, 100%, 40%);">+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:</span><br><span style="color: hsl(120, 100%, 40%);">+ PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.</span><br><span> **/</span><br><span> UINT8 PpmIrmSetting;</span><br><span> </span><br><span>@@ -3032,11 +3032,23 @@</span><br><span> **/</span><br><span> UINT8 MaxRingRatioLimit;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x08A5 - ReservedCpuPostMemTest</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateAutoDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b></span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 C3StateUnDemotion;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x08A7 - ReservedCpuPostMemTest</span><br><span> Reserved for CPU Post-Mem Test</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedCpuPostMemTest[21];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedCpuPostMemTest[19];</span><br><span> </span><br><span> /** Offset 0x08BA - SgxSinitDataFromTpm</span><br><span> SgxSinitDataFromTpm default values</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h</span><br><span>index 941a891..e2a3e09 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h</span><br><span>@@ -1,288 +1,288 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/** @file</span><br><span style="color: hsl(0, 100%, 40%);">- This file contains definitions required for creation of</span><br><span style="color: hsl(0, 100%, 40%);">- Memory S3 Save data, Memory Info data and Memory Platform</span><br><span style="color: hsl(0, 100%, 40%);">- data hobs.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-@copyright</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL CONFIDENTIAL</span><br><span style="color: hsl(0, 100%, 40%);">- Copyright 1999 - 2018 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- The source code contained or described herein and all documents related to the</span><br><span style="color: hsl(0, 100%, 40%);">- source code ("Material") are owned by Intel Corporation or its suppliers or</span><br><span style="color: hsl(0, 100%, 40%);">- licensors. Title to the Material remains with Intel Corporation or its suppliers</span><br><span style="color: hsl(0, 100%, 40%);">- and licensors. The Material may contain trade secrets and proprietary and</span><br><span style="color: hsl(0, 100%, 40%);">- confidential information of Intel Corporation and its suppliers and licensors,</span><br><span style="color: hsl(0, 100%, 40%);">- and is protected by worldwide copyright and trade secret laws and treaty</span><br><span style="color: hsl(0, 100%, 40%);">- provisions. No part of the Material may be used, copied, reproduced, modified,</span><br><span style="color: hsl(0, 100%, 40%);">- published, uploaded, posted, transmitted, distributed, or disclosed in any way</span><br><span style="color: hsl(0, 100%, 40%);">- without Intel's prior express written permission.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- No license under any patent, copyright, trade secret or other intellectual</span><br><span style="color: hsl(0, 100%, 40%);">- property right is granted to or conferred upon you by disclosure or delivery</span><br><span style="color: hsl(0, 100%, 40%);">- of the Materials, either expressly, by implication, inducement, estoppel or</span><br><span style="color: hsl(0, 100%, 40%);">- otherwise. Any license under such intellectual property rights must be</span><br><span style="color: hsl(0, 100%, 40%);">- express and approved by Intel in writing.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Unless otherwise agreed by Intel in writing, you may not remove or alter</span><br><span style="color: hsl(0, 100%, 40%);">- this notice or any other notice embedded in Materials by Intel or</span><br><span style="color: hsl(0, 100%, 40%);">- Intel's suppliers or licensors in any way.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- This file contains an 'Intel Peripheral Driver' and is uniquely identified as</span><br><span style="color: hsl(0, 100%, 40%);">- "Intel Reference Module" and is licensed for Intel CPUs and chipsets under</span><br><span style="color: hsl(0, 100%, 40%);">- the terms of your license agreement with Intel or your vendor. This file may</span><br><span style="color: hsl(0, 100%, 40%);">- be modified by the user, subject to additional terms of the license agreement.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-@par Specification Reference:</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _MEM_INFO_HOB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _MEM_INFO_HOB_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <Uefi/UefiMultiPhase.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <Pi/PiBootMode.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <Pi/PiHob.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack (push, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-extern EFI_GUID gSiMemoryS3DataGuid;</span><br><span style="color: hsl(0, 100%, 40%);">-extern EFI_GUID gSiMemoryInfoDataGuid;</span><br><span style="color: hsl(0, 100%, 40%);">-extern EFI_GUID gSiMemoryPlatformDataGuid;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_NODE 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_CH 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_DIMM 2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Host reset states from MRC.</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-#define WARM_BOOT 2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define R_MC_CHNL_RANK_PRESENT 0x7C</span><br><span style="color: hsl(0, 100%, 40%);">-#define B_RANK0_PRS BIT0</span><br><span style="color: hsl(0, 100%, 40%);">-#define B_RANK1_PRS BIT1</span><br><span style="color: hsl(0, 100%, 40%);">-#define B_RANK2_PRS BIT4</span><br><span style="color: hsl(0, 100%, 40%);">-#define B_RANK3_PRS BIT5</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Defines taken from MRC so avoid having to include MrcInterface.h</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// Matches MAX_SPD_SAVE define in MRC</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MAX_SPD_SAVE</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_SPD_SAVE 29</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// MRC version description.</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Major; ///< Major version number</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Minor; ///< Minor version number</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Rev; ///< Revision number</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Build; ///< Build number</span><br><span style="color: hsl(0, 100%, 40%);">-} SiMrcVersion;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// Matches MrcChannelSts enum in MRC</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CHANNEL_NOT_PRESENT</span><br><span style="color: hsl(0, 100%, 40%);">-#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CHANNEL_DISABLED</span><br><span style="color: hsl(0, 100%, 40%);">-#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CHANNEL_PRESENT</span><br><span style="color: hsl(0, 100%, 40%);">-#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// Matches MrcDimmSts enum in MRC</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef DIMM_ENABLED</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef DIMM_DISABLED</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef DIMM_PRESENT</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef DIMM_NOT_PRESENT</span><br><span style="color: hsl(0, 100%, 40%);">-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// Matches MrcBootMode enum in MRC</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef bmCold</span><br><span style="color: hsl(0, 100%, 40%);">-#define bmCold 0 // Cold boot</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef bmWarm</span><br><span style="color: hsl(0, 100%, 40%);">-#define bmWarm 1 // Warm boot</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef bmS3</span><br><span style="color: hsl(0, 100%, 40%);">-#define bmS3 2 // S3 resume</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef bmFast</span><br><span style="color: hsl(0, 100%, 40%);">-#define bmFast 3 // Fast boot</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// Matches MrcDdrType enum in MRC</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MRC_DDR_TYPE_DDR4</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRC_DDR_TYPE_DDR4 0</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MRC_DDR_TYPE_DDR3</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRC_DDR_TYPE_DDR3 1</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MRC_DDR_TYPE_LPDDR3</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRC_DDR_TYPE_LPDDR3 2</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CPU_CFL//CNL</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MRC_DDR_TYPE_LPDDR4</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRC_DDR_TYPE_LPDDR4 3</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#else//CFL</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef MRC_DDR_TYPE_UNKNOWN</span><br><span style="color: hsl(0, 100%, 40%);">-#define MRC_DDR_TYPE_UNKNOWN 3</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-#endif//CPU_CFL-endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_PROFILE_NUM 4 // number of memory profiles supported</span><br><span style="color: hsl(0, 100%, 40%);">-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-// DIMM timings</span><br><span style="color: hsl(0, 100%, 40%);">-//</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 tCK; ///< Memory cycle time, in femtoseconds.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.</span><br><span style="color: hsl(0, 100%, 40%);">-} MRC_CH_TIMING;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.</span><br><span style="color: hsl(0, 100%, 40%);">-} MRC_TA_TIMING;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-/// Memory SMBIOS & OC Memory Data Hob</span><br><span style="color: hsl(0, 100%, 40%);">-///</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DimmId;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 DimmCapacity; ///< DIMM size in MBytes.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 MfgId;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RankInDimm; ///< The number of ranks in this DIMM.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.</span><br><span style="color: hsl(0, 100%, 40%);">-} DIMM_INFO;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Status; ///< Indicates whether this channel should be used.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ChannelId;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.</span><br><span style="color: hsl(0, 100%, 40%);">- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.</span><br><span style="color: hsl(0, 100%, 40%);">-} CHANNEL_INFO;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Status; ///< Indicates whether this controller should be used.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DeviceId; ///< The PCI device id of this memory controller.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RevisionId; ///< The PCI revision id of this memory controller.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.</span><br><span style="color: hsl(0, 100%, 40%);">- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">-} CONTROLLER_INFO;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Revision;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 DataWidth; ///< Data width, in bits, of this memory device</span><br><span style="color: hsl(0, 100%, 40%);">- /** As defined in SMBIOS 3.0 spec</span><br><span style="color: hsl(0, 100%, 40%);">- Section 7.18.2 and Table 75</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)</span><br><span style="color: hsl(0, 100%, 40%);">- /** As defined in SMBIOS 3.0 spec</span><br><span style="color: hsl(0, 100%, 40%);">- Section 7.17.3 and Table 72</span><br><span style="color: hsl(0, 100%, 40%);">- **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ErrorCorrectionType;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- SiMrcVersion Version;</span><br><span style="color: hsl(0, 100%, 40%);">- BOOLEAN EccSupport;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 MemoryProfile;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TotalPhysicalMemorySize;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Ratio;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 RefClk;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 VddVoltage[MAX_PROFILE_NUM];</span><br><span style="color: hsl(0, 100%, 40%);">- CONTROLLER_INFO Controller[MAX_NODE];</span><br><span style="color: hsl(0, 100%, 40%);">-} MEMORY_INFO_DATA_HOB;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/**</span><br><span style="color: hsl(0, 100%, 40%);">- Memory Platform Data Hob</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- <b>Revision 1:</b></span><br><span style="color: hsl(0, 100%, 40%);">- - Initial version.</span><br><span style="color: hsl(0, 100%, 40%);">- <b>Revision 2:</b></span><br><span style="color: hsl(0, 100%, 40%);">- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Revision;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Reserved[3];</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 BootMode;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TsegSize;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 TsegBase;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PrmrrSize;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PrmrrBase;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GttBase;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 MmioSize;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 PciEBaseAddress;</span><br><span style="color: hsl(0, 100%, 40%);">-#ifdef CPU_CFL</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GdxcIotBase;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GdxcIotSize;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GdxcMotBase;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GdxcMotSize;</span><br><span style="color: hsl(0, 100%, 40%);">-#endif //CPU_CFL</span><br><span style="color: hsl(0, 100%, 40%);">-} MEMORY_PLATFORM_DATA;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- EFI_HOB_GUID_TYPE EfiHobGuidType;</span><br><span style="color: hsl(0, 100%, 40%);">- MEMORY_PLATFORM_DATA Data;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 *Buffer;</span><br><span style="color: hsl(0, 100%, 40%);">-} MEMORY_PLATFORM_DATA_HOB;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#pragma pack (pop)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif // _MEM_INFO_HOB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+/** @file
</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains definitions required for creation of
</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory S3 Save data, Memory Info data and Memory Platform
</span><br><span style="color: hsl(120, 100%, 40%);">+ data hobs.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+@copyright
</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL CONFIDENTIAL
</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright 1999 - 2018 Intel Corporation.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ The source code contained or described herein and all documents related to the
</span><br><span style="color: hsl(120, 100%, 40%);">+ source code ("Material") are owned by Intel Corporation or its suppliers or
</span><br><span style="color: hsl(120, 100%, 40%);">+ licensors. Title to the Material remains with Intel Corporation or its suppliers
</span><br><span style="color: hsl(120, 100%, 40%);">+ and licensors. The Material may contain trade secrets and proprietary and
</span><br><span style="color: hsl(120, 100%, 40%);">+ confidential information of Intel Corporation and its suppliers and licensors,
</span><br><span style="color: hsl(120, 100%, 40%);">+ and is protected by worldwide copyright and trade secret laws and treaty
</span><br><span style="color: hsl(120, 100%, 40%);">+ provisions. No part of the Material may be used, copied, reproduced, modified,
</span><br><span style="color: hsl(120, 100%, 40%);">+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
</span><br><span style="color: hsl(120, 100%, 40%);">+ without Intel's prior express written permission.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ No license under any patent, copyright, trade secret or other intellectual
</span><br><span style="color: hsl(120, 100%, 40%);">+ property right is granted to or conferred upon you by disclosure or delivery
</span><br><span style="color: hsl(120, 100%, 40%);">+ of the Materials, either expressly, by implication, inducement, estoppel or
</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise. Any license under such intellectual property rights must be
</span><br><span style="color: hsl(120, 100%, 40%);">+ express and approved by Intel in writing.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ Unless otherwise agreed by Intel in writing, you may not remove or alter
</span><br><span style="color: hsl(120, 100%, 40%);">+ this notice or any other notice embedded in Materials by Intel or
</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel's suppliers or licensors in any way.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
</span><br><span style="color: hsl(120, 100%, 40%);">+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms of your license agreement with Intel or your vendor. This file may
</span><br><span style="color: hsl(120, 100%, 40%);">+ be modified by the user, subject to additional terms of the license agreement.
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+@par Specification Reference:
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MEM_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MEM_INFO_HOB_H_
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Uefi/UefiMultiPhase.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiBootMode.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+#include <Pi/PiHob.h>
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (push, 1)
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryS3DataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryInfoDataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+extern EFI_GUID gSiMemoryPlatformDataGuid;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_NODE 1
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_CH 2
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_DIMM 2
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Host reset states from MRC.
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+#define WARM_BOOT 2
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_MC_CHNL_RANK_PRESENT 0x7C
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK0_PRS BIT0
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK1_PRS BIT1
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK2_PRS BIT4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define B_RANK3_PRS BIT5
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Defines taken from MRC so avoid having to include MrcInterface.h
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MAX_SPD_SAVE define in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MAX_SPD_SAVE
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_SPD_SAVE 29
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// MRC version description.
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Major; ///< Major version number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Minor; ///< Minor version number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Rev; ///< Revision number
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Build; ///< Build number
</span><br><span style="color: hsl(120, 100%, 40%);">+} SiMrcVersion;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcChannelSts enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_NOT_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_DISABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CHANNEL_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDimmSts enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_ENABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_DISABLED
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef DIMM_NOT_PRESENT
</span><br><span style="color: hsl(120, 100%, 40%);">+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcBootMode enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmCold
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmCold 0 // Cold boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmWarm
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmWarm 1 // Warm boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmS3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmS3 2 // S3 resume
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef bmFast
</span><br><span style="color: hsl(120, 100%, 40%);">+#define bmFast 3 // Fast boot
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// Matches MrcDdrType enum in MRC
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR4 0
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_DDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR3 1
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR3 2
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CPU_CFL//CNL
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_LPDDR4
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR4 3
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#else//CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef MRC_DDR_TYPE_UNKNOWN
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_UNKNOWN 3
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif//CPU_CFL-endif
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+// DIMM timings
</span><br><span style="color: hsl(120, 100%, 40%);">+//
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_CH_TIMING;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
</span><br><span style="color: hsl(120, 100%, 40%);">+} MRC_TA_TIMING;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+/// Memory SMBIOS & OC Memory Data Hob
</span><br><span style="color: hsl(120, 100%, 40%);">+///
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MfgId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
</span><br><span style="color: hsl(120, 100%, 40%);">+} DIMM_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this channel should be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelId;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
</span><br><span style="color: hsl(120, 100%, 40%);">+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
</span><br><span style="color: hsl(120, 100%, 40%);">+} CHANNEL_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Status; ///< Indicates whether this controller should be used.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
</span><br><span style="color: hsl(120, 100%, 40%);">+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+ MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
</span><br><span style="color: hsl(120, 100%, 40%);">+} CONTROLLER_INFO;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec
</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.18.2 and Table 75
</span><br><span style="color: hsl(120, 100%, 40%);">+ **/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
</span><br><span style="color: hsl(120, 100%, 40%);">+ /** As defined in SMBIOS 3.0 spec
</span><br><span style="color: hsl(120, 100%, 40%);">+ Section 7.17.3 and Table 72
</span><br><span style="color: hsl(120, 100%, 40%);">+ **/
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ErrorCorrectionType;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ SiMrcVersion Version;
</span><br><span style="color: hsl(120, 100%, 40%);">+ BOOLEAN EccSupport;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 MemoryProfile;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TotalPhysicalMemorySize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Ratio;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 RefClk;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VddVoltage[MAX_PROFILE_NUM];
</span><br><span style="color: hsl(120, 100%, 40%);">+ CONTROLLER_INFO Controller[MAX_NODE];
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_INFO_DATA_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+/**
</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory Platform Data Hob
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 1:</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ - Initial version.
</span><br><span style="color: hsl(120, 100%, 40%);">+ <b>Revision 2:</b>
</span><br><span style="color: hsl(120, 100%, 40%);">+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
</span><br><span style="color: hsl(120, 100%, 40%);">+**/
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Revision;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[3];
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 BootMode;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 TsegBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PrmrrBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GttBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 MmioSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 PciEBaseAddress;
</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef CPU_CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcIotSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotBase;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GdxcMotSize;
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif //CPU_CFL
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct {
</span><br><span style="color: hsl(120, 100%, 40%);">+ EFI_HOB_GUID_TYPE EfiHobGuidType;
</span><br><span style="color: hsl(120, 100%, 40%);">+ MEMORY_PLATFORM_DATA Data;
</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 *Buffer;
</span><br><span style="color: hsl(120, 100%, 40%);">+} MEMORY_PLATFORM_DATA_HOB;
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#pragma pack (pop)
</span><br><span style="color: hsl(120, 100%, 40%);">+
</span><br><span style="color: hsl(120, 100%, 40%);">+#endif // _MEM_INFO_HOB_H_
</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25219">change 25219</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25219"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie2e9ad53afbad931c494beb9c02de1f717718a37 </div>
<div style="display:none"> Gerrit-Change-Number: 25219 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>