[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25142


Change subject: soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code
......................................................................

soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code

Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. As UART
also needs AOAC, it's better to program all AOAC devices before calling any
device initialization, then do the UART initialization (without the AOAC
initialization, but waiting AOAC completion) and finally do a check/loop for
all other AOAC devices. Create a procedure that initializes all AOAC devices
in a table, then call this new procedure before the call to initialize the
UART. Then change all procedures that initialize some AOAC by moving the
devices to the table and removing AOAC initialization code.

BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.

Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 29 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25142/1

diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 3eff5eb..f85644c 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -73,6 +73,7 @@
 		bootblock_soc_init(); /* APs will not return */
 
 	bootblock_fch_early_init();
+	enable_aoac_devices();
 
 	post_code(0x90);
 	if (CONFIG_STONEYRIDGE_UART)
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index cccdf97..6cc1c79 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -342,6 +342,7 @@
 	uint8_t control;
 };
 
+void enable_aoac_devices(void);
 void sb_enable_rom(void);
 void configure_stoneyridge_uart(void);
 void configure_stoneyridge_i2c(void);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 367c565..f028d1a 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -32,6 +32,23 @@
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
 
+/*
+ * Table of devices that need their AOAC registers enabled and waited
+ * upon (usually about .55 milliseconds). Instead of individual delays
+ * waiting for each device to become available, a single delay will be
+ * executed at configure_stoneyridge_uart(). All other devices need only
+ * to verify if their AOAC is already enabled, and do a minimal delay
+ * if needed.
+ */
+static int aoac_devices[] = {
+	(FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
+	FCH_AOAC_D3_CONTROL_AMBA,
+	FCH_AOAC_D3_CONTROL_I2C0,
+	FCH_AOAC_D3_CONTROL_I2C1,
+	FCH_AOAC_D3_CONTROL_I2C2,
+	FCH_AOAC_D3_CONTROL_I2C3
+};
+
 static int is_sata_config(void)
 {
 	return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde)
@@ -296,15 +313,18 @@
 		return false;
 }
 
+void enable_aoac_devices(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(aoac_devices); i++)
+		power_on_aoac_device(aoac_devices[i]);
+}
+
 void configure_stoneyridge_uart(void)
 {
 	bool status;
 
-	/* Power on the UART and AMBA devices */
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_UART0
-			+ CONFIG_UART_FOR_CONSOLE * 2);
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_AMBA);
-
 	/* Set the GPIO mux to UART */
 	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
 	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
@@ -324,19 +344,14 @@
 {
 	bool status;
 
-	/* Power on the I2C devices */
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0);
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1);
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2);
-	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3);
-
 	/* Wait for the I2C devices to indicate power and clock OK */
 	do {
-		udelay(100);
 		status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);
 		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);
 		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);
 		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);
+		if (!status)
+			udelay(10);
 	} while (!status);
 }
 

-- 
To view, visit https://review.coreboot.org/25142
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Gerrit-Change-Number: 25142
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180313/8a4aa97f/attachment-0001.html>