<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25142">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Create AOAC initialization code<br><br>Devices that need to have their AOAC register enabled do have a delay before<br>they become available. Currently each device has their own wait loop. As UART<br>also needs AOAC, it's better to program all AOAC devices before calling any<br>device initialization, then do the UART initialization (without the AOAC<br>initialization, but waiting AOAC completion) and finally do a check/loop for<br>all other AOAC devices. Create a procedure that initializes all AOAC devices<br>in a table, then call this new procedure before the call to initialize the<br>UART. Then change all procedures that initialize some AOAC by moving the<br>devices to the table and removing AOAC initialization code.<br><br>BUG=b:74416098<br>TEST=Build and boot kahlee checking that UART is sending debug messages out.<br><br>Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>3 files changed, 29 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25142/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 3eff5eb..f85644c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -73,6 +73,7 @@</span><br><span> bootblock_soc_init(); /* APs will not return */</span><br><span> </span><br><span> bootblock_fch_early_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_aoac_devices();</span><br><span> </span><br><span> post_code(0x90);</span><br><span> if (CONFIG_STONEYRIDGE_UART)</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index cccdf97..6cc1c79 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -342,6 +342,7 @@</span><br><span> uint8_t control;</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void enable_aoac_devices(void);</span><br><span> void sb_enable_rom(void);</span><br><span> void configure_stoneyridge_uart(void);</span><br><span> void configure_stoneyridge_i2c(void);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 367c565..f028d1a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -32,6 +32,23 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <agesa_headers.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Table of devices that need their AOAC registers enabled and waited</span><br><span style="color: hsl(120, 100%, 40%);">+ * upon (usually about .55 milliseconds). Instead of individual delays</span><br><span style="color: hsl(120, 100%, 40%);">+ * waiting for each device to become available, a single delay will be</span><br><span style="color: hsl(120, 100%, 40%);">+ * executed at configure_stoneyridge_uart(). All other devices need only</span><br><span style="color: hsl(120, 100%, 40%);">+ * to verify if their AOAC is already enabled, and do a minimal delay</span><br><span style="color: hsl(120, 100%, 40%);">+ * if needed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static int aoac_devices[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_AOAC_D3_CONTROL_AMBA,</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_AOAC_D3_CONTROL_I2C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_AOAC_D3_CONTROL_I2C1,</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_AOAC_D3_CONTROL_I2C2,</span><br><span style="color: hsl(120, 100%, 40%);">+ FCH_AOAC_D3_CONTROL_I2C3</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static int is_sata_config(void)</span><br><span> {</span><br><span> return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde)</span><br><span>@@ -296,15 +313,18 @@</span><br><span> return false;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void enable_aoac_devices(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < ARRAY_SIZE(aoac_devices); i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(aoac_devices[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void configure_stoneyridge_uart(void)</span><br><span> {</span><br><span> bool status;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Power on the UART and AMBA devices */</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_UART0</span><br><span style="color: hsl(0, 100%, 40%);">- + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_AMBA);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set the GPIO mux to UART */</span><br><span> write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);</span><br><span> write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);</span><br><span>@@ -324,19 +344,14 @@</span><br><span> {</span><br><span> bool status;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Power on the I2C devices */</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0);</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1);</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2);</span><br><span style="color: hsl(0, 100%, 40%);">- power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Wait for the I2C devices to indicate power and clock OK */</span><br><span> do {</span><br><span style="color: hsl(0, 100%, 40%);">- udelay(100);</span><br><span> status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);</span><br><span> status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);</span><br><span> status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);</span><br><span> status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!status)</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(10);</span><br><span> } while (!status);</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25142">change 25142</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 </div>
<div style="display:none"> Gerrit-Change-Number: 25142 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>