[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add VT-d and VMX programming

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25118


Change subject: soc/intel/cannonlake: Add VT-d and VMX programming
......................................................................

soc/intel/cannonlake: Add VT-d and VMX programming

Add FSP option to enable/disable VT-d(Intel Virtualization Technology
for Directed I/O) and VMX(Virtual Machine Extensions), VMX will be
disabled once VT-d got disabled.

Bug=b.73655383
TEST=Build and flash image on meowth board with debug build FSP, in
serial log search for "VMXEnable" and "VtdDiable".

Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/romstage.c
3 files changed, 10 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/25118/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 2187f90..9c78b44 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -180,6 +180,7 @@
 {
 	int i;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
+	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
 	const struct device *dev = SA_DEV_ROOT;
 	config_t *config = dev->chip_info;
 
@@ -289,6 +290,9 @@
 	 * 3 = GT unsliced,  4 = GT sliced */
 	for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
 		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
+
+	/* Vt-D config */
+	tconfig->VtdDisable = config->VtdDisable;
 }
 
 /* Mainboard GPIO Configuration */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 5e70fae..a9d82fb 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -275,6 +275,9 @@
 
 	/* Enable Pch iSCLK */
 	uint8_t pch_isclk;
+
+	/* Vt-D Disable */
+	uint8_t VtdDisable;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 759c2c9..a9027a7 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -169,6 +169,9 @@
 	/* Disable Cpu Ratio Override temporary. */
 	m_cfg->CpuRatio = 0;
 	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+	/* Disable Vmx if Vt-d is already disabled */
+	if (config->VtdDisable)
+		m_cfg->VmxEnable = 0;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e
Gerrit-Change-Number: 25118
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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