<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25118">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add VT-d and VMX programming<br><br>Add FSP option to enable/disable VT-d(Intel Virtualization Technology<br>for Directed I/O) and VMX(Virtual Machine Extensions), VMX will be<br>disabled once VT-d got disabled.<br><br>Bug=b.73655383<br>TEST=Build and flash image on meowth board with debug build FSP, in<br>serial log search for "VMXEnable" and "VtdDiable".<br><br>Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>3 files changed, 10 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/25118/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 2187f90..9c78b44 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -180,6 +180,7 @@</span><br><span> {</span><br><span> int i;</span><br><span> FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;</span><br><span> const struct device *dev = SA_DEV_ROOT;</span><br><span> config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -289,6 +290,9 @@</span><br><span> * 3 = GT unsliced, 4 = GT sliced */</span><br><span> for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)</span><br><span> fill_vr_domain_config(params, i, &config->domain_vr_config[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Vt-D config */</span><br><span style="color: hsl(120, 100%, 40%);">+ tconfig->VtdDisable = config->VtdDisable;</span><br><span> }</span><br><span> </span><br><span> /* Mainboard GPIO Configuration */</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 5e70fae..a9d82fb 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -275,6 +275,9 @@</span><br><span> </span><br><span> /* Enable Pch iSCLK */</span><br><span> uint8_t pch_isclk;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Vt-D Disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t VtdDisable;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_cannonlake_config config_t;</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index 759c2c9..a9027a7 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -169,6 +169,9 @@</span><br><span> /* Disable Cpu Ratio Override temporary. */</span><br><span> m_cfg->CpuRatio = 0;</span><br><span> m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable Vmx if Vt-d is already disabled */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->VtdDisable)</span><br><span style="color: hsl(120, 100%, 40%);">+ m_cfg->VmxEnable = 0;</span><br><span> }</span><br><span> </span><br><span> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25118">change 25118</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25118"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e </div>
<div style="display:none"> Gerrit-Change-Number: 25118 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>