[coreboot-gerrit] Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Add vboot support
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Mon Mar 12 16:56:05 CET 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25109
Change subject: mb/cavium/cn8100_sff_evb: Add vboot support
......................................................................
mb/cavium/cn8100_sff_evb: Add vboot support
Add VBOOT support with a single A partition.
Tested on CN8100 without TPM.
Change-Id: Icb5395e56203fca4a03f2e9a47c21e772ad9ae79
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/mainboard/cavium/cn8100_sff_evb/Kconfig
M src/mainboard/cavium/cn8100_sff_evb/Makefile.inc
M src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd
M src/mainboard/cavium/cn8100_sff_evb/memlayout.ld
M src/soc/cavium/cn81xx/Kconfig
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/cavium/common/Makefile.inc
7 files changed, 57 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25109/1
diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig
index c900825..2dae1d00 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig
+++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig
@@ -34,9 +34,11 @@
# select SPI_FLASH_MICRON
select SPI_FLASH_STMICRO
-#config VBOOT
-# select EC_GOOGLE_CHROMEEC_SWITCHES
-# select VBOOT_VBNV_FLASH
+config VBOOT
+ select VBOOT_VBNV_FLASH
+ select GBB_FLAG_DISABLE_LID_SHUTDOWN
+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc
index 797ffc9..06d8ca3 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc
+++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc
@@ -32,6 +32,10 @@
ramstage-y += memlayout.ld
ramstage-y += reset.c
+verstage-y += reset.c
+verstage-y += memlayout.ld
+
+
MB_DIR = src/mainboard/$(MAINBOARDDIR)
DTB = sff8104.dtb
build/$(DTB):
diff --git a/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd b/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd
index 3720407..8920f46 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd
+++ b/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd
@@ -1,30 +1,27 @@
FLASH at 0x0 16M {
- WP_RO at 0x0 0x400000 {
- RO_SECTION at 0x0 0x200000 {
+ WP_RO at 0x0 0x700000 {
+ RO_SECTION at 0x0 0x6e0000 {
# bootblock includes trusted/non-trusted CLIB, CSIB,
# and BL1FWs packaged in
# src/soc/cavium/cn81xx/Makefile.inc.
BOOTBLOCK at 0 0x80000
FMAP at 0x90000 0x1000
- COREBOOT(CBFS)@0x100000 0x100000
+ GBB at 0xa0000 0x4ef00
+ RO_FRID at 0xeef00 0x100
+ COREBOOT(CBFS)@0x100000 0x5e0000
}
+ RO_VPD at 0x6e0000 0x10000
}
- RW_SECTION_A at 0x400000 0xe8000 {
- VBLOCK_A at 0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0xe5f00
- RW_FWID_A at 0xe7f00 0x100
- }
- RW_UNUSED at 0x4e8000 0x8000
- RW_SECTION_B at 0x4f0000 0xe8000 {
- VBLOCK_B at 0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0xe5f00
- RW_FWID_B at 0xe7f00 0x100
- }
- RW_ELOG at 0x5d8000 0x1000
- RW_SHARED at 0x5e0000 0x10000 {
- SHARED_DATA at 0x0 0x10000
- }
- RW_NVRAM at 0x5f0000 0x10000
-# RW_LEGACY(CBFS)@0x600000 0x200000
- CONSOLE at 0xf00000 0x100000
+ RW_VPD at 0x700000 0x8000
+ RW_ELOG at 0x708000 0x1000
+ RW_UNUSED at 0x709000 0x7000
+ RW_SHARED at 0x710000 0x10000 {
+ SHARED_DATA at 0x0 0x10000
+ }
+
+ RW_SECTION_A at 0x800000 0x600000 {
+ VBLOCK_A at 0x0 0x2000
+ FW_MAIN_A(CBFS)@0x2000 0x5fdf00
+ RW_FWID_A at 0x5fff00 0x100
+ }
}
diff --git a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld
index 9349362..2c33306 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld
+++ b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld
@@ -1 +1,14 @@
- #include <soc/memlayout.ld>
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/memlayout.ld>
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index 0693033..3ea007b 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -24,11 +24,10 @@
if SOC_CAVIUM_CN81XX
-#config VBOOT
-# select VBOOT_SEPARATE_VERSTAGE
-# select VBOOT_RETURN_FROM_VERSTAGE
-# select VBOOT_OPROM_MATTERS
-# select VBOOT_STARTS_IN_BOOTBLOCK
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_RETURN_FROM_VERSTAGE
+ select VBOOT_STARTS_IN_BOOTBLOCK
config PMIC_BUS
int
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index 949702d..9169ffa 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -32,11 +32,6 @@
/* SYMBOL(_devicetree, 0x30000 - 0x4096) */
- /*
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CB000, 92K)
- VBOOT2_WORK(0XFF8E2000, 12K)
- */
-
/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
SRAM_START(BOOTROM_OFFSET)
STACK(BOOTROM_OFFSET, 16K)
@@ -46,10 +41,13 @@
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
- TTB(BOOTROM_OFFSET + 0x30000, 64K)
- ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
- SRAM_END(BOOTROM_OFFSET + 0x80000)
+ ROMSTAGE(BOOTROM_OFFSET + 0x30000, 256K)
+ OVERLAP_VERSTAGE_ROMSTAGE(BOOTROM_OFFSET + 0x70000, 128K)
+ VBOOT2_WORK(BOOTROM_OFFSET + 0x90000, 32K)
+ SRAM_END(BOOTROM_OFFSET + 0x98000)
- POSTRAM_CBFS_CACHE(0x2000000, 1M)
- RAMSTAGE(0x3000000, 256K)
+ RAMSTAGE(0x2000000, 512K)
+ POSTRAM_CBFS_CACHE(0x3000000, 16M)
+
+ TTB(0x20000000, 2M)
}
diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc
index 5f47a1d..e225575 100644
--- a/src/soc/cavium/common/Makefile.inc
+++ b/src/soc/cavium/common/Makefile.inc
@@ -43,6 +43,10 @@
ramstage-y += uart.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+verstage-y += spi.c
+verstage-y += timer.c
+verstage-$(CONFIG_DRIVERS_UART) += uart.c
+
CPPFLAGS_common += -Isrc/soc/cavium/common/include
ROM_HEADER_BIN := $(objgenerated)/rom_header.bin
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icb5395e56203fca4a03f2e9a47c21e772ad9ae79
Gerrit-Change-Number: 25109
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
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