<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25109">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/cavium/cn8100_sff_evb: Add vboot support<br><br>Add VBOOT support with a single A partition.<br>Tested on CN8100 without TPM.<br><br>Change-Id: Icb5395e56203fca4a03f2e9a47c21e772ad9ae79<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/mainboard/cavium/cn8100_sff_evb/Kconfig<br>M src/mainboard/cavium/cn8100_sff_evb/Makefile.inc<br>M src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd<br>M src/mainboard/cavium/cn8100_sff_evb/memlayout.ld<br>M src/soc/cavium/cn81xx/Kconfig<br>M src/soc/cavium/cn81xx/include/soc/memlayout.ld<br>M src/soc/cavium/common/Makefile.inc<br>7 files changed, 57 insertions(+), 40 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25109/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfig</span><br><span>index c900825..2dae1d00 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/Kconfig</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/Kconfig</span><br><span>@@ -34,9 +34,11 @@</span><br><span> # select SPI_FLASH_MICRON</span><br><span> select SPI_FLASH_STMICRO</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#config VBOOT</span><br><span style="color: hsl(0, 100%, 40%);">-# select EC_GOOGLE_CHROMEEC_SWITCHES</span><br><span style="color: hsl(0, 100%, 40%);">-# select VBOOT_VBNV_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_VBNV_FLASH</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_LID_SHUTDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC</span><br><span style="color: hsl(120, 100%, 40%);">+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC</span><br><span> </span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc</span><br><span>index 797ffc9..06d8ca3 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc</span><br><span>@@ -32,6 +32,10 @@</span><br><span> ramstage-y += memlayout.ld</span><br><span> ramstage-y += reset.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += reset.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += memlayout.ld</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> MB_DIR = src/mainboard/$(MAINBOARDDIR)</span><br><span> DTB = sff8104.dtb</span><br><span> build/$(DTB):</span><br><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd b/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd</span><br><span>index 3720407..8920f46 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/chromeos.fmd</span><br><span>@@ -1,30 +1,27 @@</span><br><span> FLASH@0x0 16M {</span><br><span style="color: hsl(0, 100%, 40%);">- WP_RO@0x0 0x400000 {</span><br><span style="color: hsl(0, 100%, 40%);">- RO_SECTION@0x0 0x200000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ WP_RO@0x0 0x700000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_SECTION@0x0 0x6e0000 {</span><br><span> # bootblock includes trusted/non-trusted CLIB, CSIB,</span><br><span> # and BL1FWs packaged in</span><br><span> # src/soc/cavium/cn81xx/Makefile.inc.</span><br><span> BOOTBLOCK@0 0x80000</span><br><span> FMAP@0x90000 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- COREBOOT(CBFS)@0x100000 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+ GBB@0xa0000 0x4ef00</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_FRID@0xeef00 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ COREBOOT(CBFS)@0x100000 0x5e0000</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ RO_VPD@0x6e0000 0x10000</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_A@0x400000 0xe8000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_A@0x0 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_A(CBFS)@0x2000 0xe5f00</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_A@0xe7f00 0x100</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_UNUSED@0x4e8000 0x8000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SECTION_B@0x4f0000 0xe8000 {</span><br><span style="color: hsl(0, 100%, 40%);">- VBLOCK_B@0x0 0x2000</span><br><span style="color: hsl(0, 100%, 40%);">- FW_MAIN_B(CBFS)@0x2000 0xe5f00</span><br><span style="color: hsl(0, 100%, 40%);">- RW_FWID_B@0xe7f00 0x100</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_ELOG@0x5d8000 0x1000</span><br><span style="color: hsl(0, 100%, 40%);">- RW_SHARED@0x5e0000 0x10000 {</span><br><span style="color: hsl(0, 100%, 40%);">- SHARED_DATA@0x0 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- RW_NVRAM@0x5f0000 0x10000</span><br><span style="color: hsl(0, 100%, 40%);">-# RW_LEGACY(CBFS)@0x600000 0x200000</span><br><span style="color: hsl(0, 100%, 40%);">- CONSOLE@0xf00000 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_VPD@0x700000 0x8000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_ELOG@0x708000 0x1000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_UNUSED@0x709000 0x7000</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SHARED@0x710000 0x10000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ SHARED_DATA@0x0 0x10000</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_SECTION_A@0x800000 0x600000 {</span><br><span style="color: hsl(120, 100%, 40%);">+ VBLOCK_A@0x0 0x2000</span><br><span style="color: hsl(120, 100%, 40%);">+ FW_MAIN_A(CBFS)@0x2000 0x5fdf00</span><br><span style="color: hsl(120, 100%, 40%);">+ RW_FWID_A@0x5fff00 0x100</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld</span><br><span>index 9349362..2c33306 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld</span><br><span>@@ -1 +1,14 @@</span><br><span style="color: hsl(0, 100%, 40%);">- #include <soc/memlayout.ld></span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/memlayout.ld></span><br><span>diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig</span><br><span>index 0693033..3ea007b 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Kconfig</span><br><span>+++ b/src/soc/cavium/cn81xx/Kconfig</span><br><span>@@ -24,11 +24,10 @@</span><br><span> </span><br><span> if SOC_CAVIUM_CN81XX</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#config VBOOT</span><br><span style="color: hsl(0, 100%, 40%);">-# select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-# select VBOOT_RETURN_FROM_VERSTAGE</span><br><span style="color: hsl(0, 100%, 40%);">-# select VBOOT_OPROM_MATTERS</span><br><span style="color: hsl(0, 100%, 40%);">-# select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+config VBOOT</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_SEPARATE_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_RETURN_FROM_VERSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VBOOT_STARTS_IN_BOOTBLOCK</span><br><span> </span><br><span> config PMIC_BUS</span><br><span> int</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>index 949702d..9169ffa 100644</span><br><span>--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld</span><br><span>@@ -32,11 +32,6 @@</span><br><span> </span><br><span> /* SYMBOL(_devicetree, 0x30000 - 0x4096) */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CB000, 92K)</span><br><span style="color: hsl(0, 100%, 40%);">- VBOOT2_WORK(0XFF8E2000, 12K)</span><br><span style="color: hsl(0, 100%, 40%);">- */ </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */</span><br><span> SRAM_START(BOOTROM_OFFSET)</span><br><span> STACK(BOOTROM_OFFSET, 16K)</span><br><span>@@ -46,10 +41,13 @@</span><br><span> PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)</span><br><span> </span><br><span> BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">- TTB(BOOTROM_OFFSET + 0x30000, 64K)</span><br><span style="color: hsl(0, 100%, 40%);">- ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)</span><br><span style="color: hsl(0, 100%, 40%);">- SRAM_END(BOOTROM_OFFSET + 0x80000)</span><br><span style="color: hsl(120, 100%, 40%);">+ ROMSTAGE(BOOTROM_OFFSET + 0x30000, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+ OVERLAP_VERSTAGE_ROMSTAGE(BOOTROM_OFFSET + 0x70000, 128K)</span><br><span style="color: hsl(120, 100%, 40%);">+ VBOOT2_WORK(BOOTROM_OFFSET + 0x90000, 32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ SRAM_END(BOOTROM_OFFSET + 0x98000)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- POSTRAM_CBFS_CACHE(0x2000000, 1M)</span><br><span style="color: hsl(0, 100%, 40%);">- RAMSTAGE(0x3000000, 256K)</span><br><span style="color: hsl(120, 100%, 40%);">+ RAMSTAGE(0x2000000, 512K)</span><br><span style="color: hsl(120, 100%, 40%);">+ POSTRAM_CBFS_CACHE(0x3000000, 16M)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ TTB(0x20000000, 2M)</span><br><span> }</span><br><span>diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc</span><br><span>index 5f47a1d..e225575 100644</span><br><span>--- a/src/soc/cavium/common/Makefile.inc</span><br><span>+++ b/src/soc/cavium/common/Makefile.inc</span><br><span>@@ -43,6 +43,10 @@</span><br><span> ramstage-y += uart.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += timer.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> CPPFLAGS_common += -Isrc/soc/cavium/common/include</span><br><span> </span><br><span> ROM_HEADER_BIN := $(objgenerated)/rom_header.bin</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25109">change 25109</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25109"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icb5395e56203fca4a03f2e9a47c21e772ad9ae79 </div>
<div style="display:none"> Gerrit-Change-Number: 25109 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>