[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable RTC write protect

[Caveh Jalali (Code Review)]

Hello caveh jalali,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/25069

to review the following change.


Change subject: soc/intel/cannonlake: Disable RTC write protect
......................................................................

soc/intel/cannonlake: Disable RTC write protect

The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we
need this memory to be writable.  We normally over-ride this in the
SoC chip init code, so we'll do the same on cannonlake.

BUG=b:71722386
BRANCH=none
TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip
all the bits.

Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b
Signed-off-by: Caveh Jalali <caveh at chromium.org>
---
M src/soc/intel/cannonlake/chip.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/25069/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 2187f90..ca2f9a3 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -200,6 +200,9 @@
 
 	mainboard_silicon_init_params(params);
 
+	/* Unlock upper 8 bytes of RTC RAM */
+	params->PchLockDownRtcMemoryLock = 0;
+
 	/* SATA */
 	params->SataEnable = config->SataEnable;
 	params->SataMode = config->SataMode;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b
Gerrit-Change-Number: 25069
Gerrit-PatchSet: 1
Gerrit-Owner: Caveh Jalali <caveh at google.com>
Gerrit-Reviewer: caveh jalali <caveh at chromium.org>
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