<p>Caveh Jalali would like caveh jalali to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25069">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Disable RTC write protect<br><br>The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we<br>need this memory to be writable.  We normally over-ride this in the<br>SoC chip init code, so we'll do the same on cannonlake.<br><br>BUG=b:71722386<br>BRANCH=none<br>TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip<br>all the bits.<br><br>Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b<br>Signed-off-by: Caveh Jalali <caveh@chromium.org><br>---<br>M src/soc/intel/cannonlake/chip.c<br>1 file changed, 3 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/25069/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 2187f90..ca2f9a3 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -200,6 +200,9 @@</span><br><span> </span><br><span>  mainboard_silicon_init_params(params);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+    /* Unlock upper 8 bytes of RTC RAM */</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchLockDownRtcMemoryLock = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   /* SATA */</span><br><span>   params->SataEnable = config->SataEnable;</span><br><span>       params->SataMode = config->SataMode;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25069">change 25069</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25069"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b </div>
<div style="display:none"> Gerrit-Change-Number: 25069 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Caveh Jalali <caveh@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: caveh jalali <caveh@chromium.org> </div>