[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Enables decoding of the COMB range to LPC based on ...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25045


Change subject: soc/intel/common: Enables decoding of the COMB range to LPC based on Kconfig
......................................................................

soc/intel/common: Enables decoding of the COMB range to LPC based on Kconfig

By default all Intel platform has enable IO decode range for COMA. With
this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
Kconfig selection.

Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/block/lpc/Kconfig
M src/soc/intel/common/block/lpc/lpc_lib.c
2 files changed, 21 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25045/1

diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig
index c384c34..27641d3 100644
--- a/src/soc/intel/common/block/lpc/Kconfig
+++ b/src/soc/intel/common/block/lpc/Kconfig
@@ -3,3 +3,11 @@
 	help
 	  Use common LPC code for platform. Only soc specific code needs to
 	  be implemented as per requirement.
+
+config SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
+	depends on SOC_INTEL_COMMON_BLOCK_LPC
+	bool
+	default n
+	help
+	  By default COMA range to LPC is enable. COMB range to LPC is optional
+	  and should select based on platform dedicated selection.
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index b4b3d1b..3570f61 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -225,15 +225,20 @@
 
 void lpc_io_setup_comm_a_b(void)
 {
-	/*
-	* Setup I/O Decode Range Register for LPC
-	* ComA Range 3F8h-3FFh [2:0]
-	* ComB Range 2F8h-2FFh [6:4]
-	*/
-	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE,
-			LPC_IOD_COMA_RANGE | LPC_IOD_COMB_RANGE);
+	/* ComA Range 3F8h-3FFh [2:0] */
+	uint16_t com_ranges = LPC_IOD_COMA_RANGE;
+	uint16_t com_enable = LPC_IOE_COMA_EN;
+
+	/* ComB Range 2F8h-2FFh [6:4] */
+	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
+		com_ranges |= LPC_IOD_COMB_RANGE;
+		com_enable |= LPC_IOE_COMB_EN;
+	}
+
+	/* Setup I/O Decode Range Register for LPC */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
 	/* Enable ComA and ComB Port */
-	lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN);
+	lpc_enable_fixed_io_ranges(com_enable);
 }
 
 static void lpc_set_gen_decode_range(

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Gerrit-Change-Number: 25045
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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