<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25045">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Enables decoding of the COMB range to LPC based on Kconfig<br><br>By default all Intel platform has enable IO decode range for COMA. With<br>this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE<br>Kconfig selection.<br><br>Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/block/lpc/Kconfig<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>2 files changed, 21 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25045/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig</span><br><span>index c384c34..27641d3 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/lpc/Kconfig</span><br><span>@@ -3,3 +3,11 @@</span><br><span>       help</span><br><span>           Use common LPC code for platform. Only soc specific code needs to</span><br><span>    be implemented as per requirement.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on SOC_INTEL_COMMON_BLOCK_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+  default n</span><br><span style="color: hsl(120, 100%, 40%);">+     help</span><br><span style="color: hsl(120, 100%, 40%);">+    By default COMA range to LPC is enable. COMB range to LPC is optional</span><br><span style="color: hsl(120, 100%, 40%);">+         and should select based on platform dedicated selection.</span><br><span>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>index b4b3d1b..3570f61 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>@@ -225,15 +225,20 @@</span><br><span> </span><br><span> void lpc_io_setup_comm_a_b(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    /*</span><br><span style="color: hsl(0, 100%, 40%);">-      * Setup I/O Decode Range Register for LPC</span><br><span style="color: hsl(0, 100%, 40%);">-       * ComA Range 3F8h-3FFh [2:0]</span><br><span style="color: hsl(0, 100%, 40%);">-    * ComB Range 2F8h-2FFh [6:4]</span><br><span style="color: hsl(0, 100%, 40%);">-    */</span><br><span style="color: hsl(0, 100%, 40%);">-      pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE,</span><br><span style="color: hsl(0, 100%, 40%);">-                  LPC_IOD_COMA_RANGE | LPC_IOD_COMB_RANGE);</span><br><span style="color: hsl(120, 100%, 40%);">+     /* ComA Range 3F8h-3FFh [2:0] */</span><br><span style="color: hsl(120, 100%, 40%);">+      uint16_t com_ranges = LPC_IOD_COMA_RANGE;</span><br><span style="color: hsl(120, 100%, 40%);">+     uint16_t com_enable = LPC_IOE_COMA_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+      /* ComB Range 2F8h-2FFh [6:4] */</span><br><span style="color: hsl(120, 100%, 40%);">+      if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {</span><br><span style="color: hsl(120, 100%, 40%);">+              com_ranges |= LPC_IOD_COMB_RANGE;</span><br><span style="color: hsl(120, 100%, 40%);">+             com_enable |= LPC_IOE_COMB_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+        }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Setup I/O Decode Range Register for LPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);</span><br><span>  /* Enable ComA and ComB Port */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+        lpc_enable_fixed_io_ranges(com_enable);</span><br><span> }</span><br><span> </span><br><span> static void lpc_set_gen_decode_range(</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25045">change 25045</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.cor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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc </div>
<div style="display:none"> Gerrit-Change-Number: 25045 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>