[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add TPM Configuration

[Garrett Kirkendall (Code Review)]

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25027


Change subject: soc/amd/stoneyridge: Add TPM Configuration
......................................................................

soc/amd/stoneyridge: Add TPM Configuration

* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 32 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25027/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index cccdf97..0483340 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -186,6 +186,11 @@
 #define LPC_MISC_CONTROL_BITS		0x78
 #define   LPC_NOHOG			BIT(0)
 
+
+#define LPC_TRUSTED_PLATFORM_MODULE	0x7c
+#define   TPM_12_EN			BIT(0)
+#define   TPM_LEGACY_EN			BIT(2)
+
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
 /*
@@ -357,6 +362,7 @@
 void sb_read_mode(u32 mode);
 void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 void sb_set_readspeed(u16 norm, u16 fast);
+void sb_tpm_decode(void);
 void sb_tpm_decode_spi(void);
 void lpc_wideio_512_window(uint16_t base);
 void lpc_wideio_16_window(uint16_t base);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 367c565..adb3fde 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -470,8 +470,34 @@
 					& ~SPI_READ_MODE_MASK) | mode);
 }
 
+/*
+ * Enable FCH to decode TPM associated Memory and IO regions
+ *
+ * Enable decoding of TPM cycles defined in TPM 1.2 spec
+ * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
+ * 0x7e and 0xef-0xee.
+ */
+void sb_tpm_decode(void)
+{
+	/* Enable TPM decoding to FCH */
+	u32 value = pci_read_config32(SOC_LPC_DEV,
+					LPC_TRUSTED_PLATFORM_MODULE);
+	value |= (TPM_12_EN | TPM_LEGACY_EN);
+	pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
+}
+
+/*
+ * Enable FCH to decode TPM associated Memory and IO regions to SPI
+ *
+ * This would be used if TPM is connectd to SPI bus like Kahlee.
+ * Assumes SPI address space is already configured via a call to sb_spibase().
+ */
 void sb_tpm_decode_spi(void)
 {
+	/* Enable TPM decoding to FCH */
+	sb_tpm_decode();
+
+	/* Route TPM accesses to SPI */
 	u32 spibase = pci_read_config32(SOC_LPC_DEV,
 					SPIROM_BASE_ADDRESS_REGISTER);
 	pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Gerrit-Change-Number: 25027
Gerrit-PatchSet: 1
Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
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