<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25027">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add TPM Configuration<br><br>* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy<br>TPM IO 0x7f-0x7e and 0xef-0xee<br>* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.<br><br>BUG=b:65442212<br>BRANCH=master<br>TEST=abuild, build Gardenia, build and boot Grunt<br><br>Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 32 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/25027/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index cccdf97..0483340 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -186,6 +186,11 @@</span><br><span> #define LPC_MISC_CONTROL_BITS 0x78</span><br><span> #define LPC_NOHOG BIT(0)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_TRUSTED_PLATFORM_MODULE 0x7c</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_12_EN BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_LEGACY_EN BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define LPC_WIDEIO2_GENERIC_PORT 0x90</span><br><span> </span><br><span> /*</span><br><span>@@ -357,6 +362,7 @@</span><br><span> void sb_read_mode(u32 mode);</span><br><span> void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);</span><br><span> void sb_set_readspeed(u16 norm, u16 fast);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_tpm_decode(void);</span><br><span> void sb_tpm_decode_spi(void);</span><br><span> void lpc_wideio_512_window(uint16_t base);</span><br><span> void lpc_wideio_16_window(uint16_t base);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 367c565..adb3fde 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -470,8 +470,34 @@</span><br><span> & ~SPI_READ_MODE_MASK) | mode);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable FCH to decode TPM associated Memory and IO regions</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable decoding of TPM cycles defined in TPM 1.2 spec</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable decoding of legacy TPM addresses: IO addresses 0x7f-</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x7e and 0xef-0xee.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_tpm_decode(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TPM decoding to FCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value = pci_read_config32(SOC_LPC_DEV,</span><br><span style="color: hsl(120, 100%, 40%);">+ LPC_TRUSTED_PLATFORM_MODULE);</span><br><span style="color: hsl(120, 100%, 40%);">+ value |= (TPM_12_EN | TPM_LEGACY_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable FCH to decode TPM associated Memory and IO regions to SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This would be used if TPM is connectd to SPI bus like Kahlee.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Assumes SPI address space is already configured via a call to sb_spibase().</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> void sb_tpm_decode_spi(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TPM decoding to FCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_tpm_decode();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Route TPM accesses to SPI */</span><br><span> u32 spibase = pci_read_config32(SOC_LPC_DEV,</span><br><span> SPIROM_BASE_ADDRESS_REGISTER);</span><br><span> pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25027">change 25027</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 </div>
<div style="display:none"> Gerrit-Change-Number: 25027 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>