[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Support I2C device enable

[Garrett Kirkendall (Code Review)]

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25026


Change subject: soc/amd/stoneyridge: Support I2C device enable
......................................................................

soc/amd/stoneyridge: Support I2C device enable

Add function to enable the stoneyridge four I2C engines.  This is in
preparation of moving the AGESA calls out of the bootblock.

BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
2 files changed, 21 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25026/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 88403e6..cccdf97 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -344,6 +344,7 @@
 
 void sb_enable_rom(void);
 void configure_stoneyridge_uart(void);
+void configure_stoneyridge_i2c(void);
 void sb_clk_output_48Mhz(void);
 void sb_disable_4dw_burst(void);
 void sb_enable(device_t dev);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index c591c69..367c565 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -320,6 +320,26 @@
 	} while (!status);
 }
 
+void configure_stoneyridge_i2c(void)
+{
+	bool status;
+
+	/* Power on the I2C devices */
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0);
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1);
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2);
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3);
+
+	/* Wait for the I2C devices to indicate power and clock OK */
+	do {
+		udelay(100);
+		status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);
+		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);
+		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);
+		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);
+	} while (!status);
+}
+
 void sb_pci_port80(void)
 {
 	u8 byte;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Gerrit-Change-Number: 25026
Gerrit-PatchSet: 1
Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
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