<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25026">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Support I2C device enable<br><br>Add function to enable the stoneyridge four I2C engines.  This is in<br>preparation of moving the AGESA calls out of the bootblock.<br><br>BUG=b:65442212<br>BRANCH=master<br>TEST=abuild, build Gardenia, build and boot Grunt<br><br>Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 21 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25026/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 88403e6..cccdf97 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -344,6 +344,7 @@</span><br><span> </span><br><span> void sb_enable_rom(void);</span><br><span> void configure_stoneyridge_uart(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_i2c(void);</span><br><span> void sb_clk_output_48Mhz(void);</span><br><span> void sb_disable_4dw_burst(void);</span><br><span> void sb_enable(device_t dev);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index c591c69..367c565 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -320,6 +320,26 @@</span><br><span>  } while (!status);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_i2c(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+  bool status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /* Power on the I2C devices */</span><br><span style="color: hsl(120, 100%, 40%);">+        power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0);</span><br><span style="color: hsl(120, 100%, 40%);">+       power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1);</span><br><span style="color: hsl(120, 100%, 40%);">+       power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2);</span><br><span style="color: hsl(120, 100%, 40%);">+       power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Wait for the I2C devices to indicate power and clock OK */</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+          udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+          status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0);</span><br><span style="color: hsl(120, 100%, 40%);">+              status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1);</span><br><span style="color: hsl(120, 100%, 40%);">+         status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2);</span><br><span style="color: hsl(120, 100%, 40%);">+         status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (!status);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void sb_pci_port80(void)</span><br><span> {</span><br><span>     u8 byte;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25026">change 25026</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25026"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826 </div>
<div style="display:none"> Gerrit-Change-Number: 25026 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>