[coreboot-gerrit] Change in coreboot[master]: Alkali: Add memory detection logic

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/25000


Change subject: Alkali: Add memory detection logic
......................................................................

Alkali: Add memory detection logic

Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3.  We do this with the PCH_MEM_CONFIG4 GPIO.

BUG=b:73514687
BRANCH=None
TEST=None

Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
M src/mainboard/google/poppy/variants/nami/memory.c
2 files changed, 12 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25000/1

diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
index 3dfe92f..98450f6 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/gpio.h
@@ -30,6 +30,7 @@
 #define GPIO_MEM_CONFIG_1	GPP_C13
 #define GPIO_MEM_CONFIG_2	GPP_C14
 #define GPIO_MEM_CONFIG_3	GPP_C15
+#define GPIO_MEM_CONFIG_4	GPP_E15
 
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE		GPE0_LAN_WAK
diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c
index dec7626..e6c169c 100644
--- a/src/mainboard/google/poppy/variants/nami/memory.c
+++ b/src/mainboard/google/poppy/variants/nami/memory.c
@@ -14,6 +14,8 @@
  */
 
 #include <baseboard/variants.h>
+#include <gpio.h>
+#include <variant/gpio.h>
 #include <string.h>
 
 /* Rcomp resistor */
@@ -31,8 +33,17 @@
 
 void variant_memory_params(struct memory_params *p)
 {
+	int pch_mem_config4 = gpio_get(GPIO_MEM_CONFIG_4);
+
+	/* default to DDR4 */
 	memset(p, 0, sizeof(*p));
 	p->type = MEMORY_DDR4;
+	p->use_sec_spd = 0;
+	if (pch_mem_config4 == 1) {
+		/* set to LPDDR3 */
+		p->type = MEMORY_LPDDR3;
+		p->use_sec_spd = 1;
+	}
 
 	/* Rcomp resistor values are different for SDP and DDP. */
 	if (ddp_bitmap & MEM_ID(variant_memory_sku())) {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Gerrit-Change-Number: 25000
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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