[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy : Get SKU_ID from EC for Nami/Vayne

[Amanda Hwang (Code Review)]

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/24996


Change subject: mb/google/poppy : Get SKU_ID from EC for Nami/Vayne
......................................................................

mb/google/poppy : Get SKU_ID from EC for Nami/Vayne

CBI abbreviates Cros Board Info.
BUG=b:74177699
BRANCH=master
TEST=Verify CPU log shows expected SKU ID on Nami.

Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75
Signed-off-by: amanda_hwang <amanda_hwang at compal.corp-partner.google.com>
---
M src/mainboard/google/poppy/ramstage.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/include/fsp20/soc/ramstage.h
3 files changed, 58 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/24996/1

diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c
index 39df3ee..3b34a96 100644
--- a/src/mainboard/google/poppy/ramstage.c
+++ b/src/mainboard/google/poppy/ramstage.c
@@ -15,9 +15,59 @@
 
 #include <baseboard/variants.h>
 #include <soc/ramstage.h>
-
+#include <ec/google/chromeec/ec.h>
+#include <string.h>
+#include <assert.h>
 #include <variant/gpio.h>
 
+#define SKU_0_Nami	0x3A7B
+#define SKU_1_Vayne	0x3A63
+#define SKU_2_Vayne	0x3A7F
+
+
+static uint16_t board_sku_id(void)
+{
+	static int sku_id = -1;
+
+	if (sku_id < 0) {
+		uint32_t id;
+		if (google_chromeec_cbi_get_sku_id(&id))
+			/* TODO: Once transition completes, raise error instead
+			   of returning gpio value which could be unintended. */
+			/* Reading from EC may succeed next time but we do not
+			   want to return different values. So, we cache the
+			   value read from GPIOs. */
+			printk(BIOS_INFO, "get sku id failed\n");
+		sku_id = id;
+	}
+
+	return sku_id;
+}
+
+
+void mainboard_devtree_update(struct device *dev)
+{
+       /* Override dev tree settings per board */
+	struct soc_intel_skylake_config *cfg = dev->chip_info;
+	uint16_t sku_id;
+	sku_id = board_sku_id();	
+
+	switch (sku_id) {
+        case SKU_0_Nami:
+			printk(BIOS_INFO, "SKU_0_Nami\n");
+			cfg->usb2_ports[5].enable = 1;//rear camera
+			cfg->usb2_ports[6].enable = 1; //front camera
+			break;
+        case SKU_1_Vayne:
+			printk(BIOS_INFO, "SKU_1_Vayne\n");
+			cfg->usb2_ports[5].enable = 0;//rear camera
+			cfg->usb2_ports[6].enable = 1; //front camera
+		break;
+	default:
+		break;
+	}
+}
+
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
 	const struct pad_config *pads;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3bc66b2..e5ffc21 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -102,6 +102,7 @@
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;
 	}
+	mainboard_devtree_update(dev);
 	config = dev->chip_info;
 
 	mainboard_silicon_init_params(params);
@@ -328,3 +329,8 @@
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+__attribute__((weak)) void mainboard_devtree_update(struct device *dev)
+{
+       /* Override dev tree settings per board */
+}
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
index 23443c3..92d7069 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -31,5 +31,6 @@
 void soc_init_pre_device(void *chip_info);
 void soc_irq_settings(FSP_SIL_UPD *params);
 const char *soc_acpi_name(const struct device *dev);
+void mainboard_devtree_update(struct device *dev);
 
 #endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75
Gerrit-Change-Number: 24996
Gerrit-PatchSet: 1
Gerrit-Owner: Amanda Hwang <amanda_hwang at compal.corp-partner.google.com>
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