<p>Amanda Hwang has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24996">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy : Get SKU_ID from EC for Nami/Vayne<br><br>CBI abbreviates Cros Board Info.<br>BUG=b:74177699<br>BRANCH=master<br>TEST=Verify CPU log shows expected SKU ID on Nami.<br><br>Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75<br>Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com><br>---<br>M src/mainboard/google/poppy/ramstage.c<br>M src/soc/intel/skylake/chip_fsp20.c<br>M src/soc/intel/skylake/include/fsp20/soc/ramstage.h<br>3 files changed, 58 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/24996/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/ramstage.c b/src/mainboard/google/poppy/ramstage.c</span><br><span>index 39df3ee..3b34a96 100644</span><br><span>--- a/src/mainboard/google/poppy/ramstage.c</span><br><span>+++ b/src/mainboard/google/poppy/ramstage.c</span><br><span>@@ -15,9 +15,59 @@</span><br><span> </span><br><span> #include <baseboard/variants.h></span><br><span> #include <soc/ramstage.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span> #include <variant/gpio.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define SKU_0_Nami 0x3A7B</span><br><span style="color: hsl(120, 100%, 40%);">+#define SKU_1_Vayne 0x3A63</span><br><span style="color: hsl(120, 100%, 40%);">+#define SKU_2_Vayne 0x3A7F</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t board_sku_id(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static int sku_id = -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sku_id < 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t id;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (google_chromeec_cbi_get_sku_id(&id))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Once transition completes, raise error instead</span><br><span style="color: hsl(120, 100%, 40%);">+ of returning gpio value which could be unintended. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reading from EC may succeed next time but we do not</span><br><span style="color: hsl(120, 100%, 40%);">+ want to return different values. So, we cache the</span><br><span style="color: hsl(120, 100%, 40%);">+ value read from GPIOs. */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "get sku id failed\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ sku_id = id;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return sku_id;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_devtree_update(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Override dev tree settings per board */</span><br><span style="color: hsl(120, 100%, 40%);">+ struct soc_intel_skylake_config *cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t sku_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ sku_id = board_sku_id(); </span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (sku_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case SKU_0_Nami:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SKU_0_Nami\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->usb2_ports[5].enable = 1;//rear camera</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->usb2_ports[6].enable = 1; //front camera</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case SKU_1_Vayne:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "SKU_1_Vayne\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->usb2_ports[5].enable = 0;//rear camera</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->usb2_ports[6].enable = 1; //front camera</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void mainboard_silicon_init_params(FSP_SIL_UPD *params)</span><br><span> {</span><br><span> const struct pad_config *pads;</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 3bc66b2..e5ffc21 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -102,6 +102,7 @@</span><br><span> printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");</span><br><span> return;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_devtree_update(dev);</span><br><span> config = dev->chip_info;</span><br><span> </span><br><span> mainboard_silicon_init_params(params);</span><br><span>@@ -328,3 +329,8 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) void mainboard_devtree_update(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Override dev tree settings per board */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h</span><br><span>index 23443c3..92d7069 100644</span><br><span>--- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h</span><br><span>@@ -31,5 +31,6 @@</span><br><span> void soc_init_pre_device(void *chip_info);</span><br><span> void soc_irq_settings(FSP_SIL_UPD *params);</span><br><span> const char *soc_acpi_name(const struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_devtree_update(struct device *dev);</span><br><span> </span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24996">change 24996</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75 </div>
<div style="display:none"> Gerrit-Change-Number: 24996 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> </div>