[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: add LPEA resources to southcluster.asl

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/24987


Change subject: soc/intel/braswell: add LPEA resources to southcluster.asl
......................................................................

soc/intel/braswell: add LPEA resources to southcluster.asl

The LPEA device memory resources, required by Windows drivers,
were not being set.  Allocate required resources per Inte'sl CHT
Tianocore reference code.

Test: boot Windows on google/edgar, observe LPEA device working properly.

Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/acpi/southcluster.asl
1 file changed, 23 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/24987/1

diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 19a58d1..f7e3168 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -153,6 +153,12 @@
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
+		/* LPEA Memory Region (0x20000000-0x201FFFFF) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
+				0x00200000,,, LMEM)
+
 		/* PCI Memory Region (Top of memory-0xfeafffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
@@ -166,6 +172,23 @@
 				0x00005000,,, TPMR)
 	})
 
+	/* Update LPEA resource area */
+	CreateDWordField (MCRS, LMEM._MIN, LMIN)
+	CreateDWordField (MCRS, LMEM._MAX, LMAX)
+	CreateDWordField (MCRS, LMEM._LEN, LLEN)
+	If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One)))
+	{
+		Store (LPFW, LMIN)
+		Store (Add (LMIN, 0x001FFFFF), LMAX)
+		Store (0x00200000, LLEN)
+	}
+	Else
+	{
+		Store (Zero, LMIN)
+		Store (Zero, LMAX)
+		Store (Zero, LLEN)
+	}
+
 	/* Update PCI resource area */
 	CreateDwordField(MCRS, PMEM._MIN, PMIN)
 	CreateDwordField(MCRS, PMEM._MAX, PMAX)

-- 
To view, visit https://review.coreboot.org/24987
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da
Gerrit-Change-Number: 24987
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180304/0b1fe453/attachment-0001.html>