<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24987">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: add LPEA resources to southcluster.asl<br><br>The LPEA device memory resources, required by Windows drivers,<br>were not being set.  Allocate required resources per Inte'sl CHT<br>Tianocore reference code.<br><br>Test: boot Windows on google/edgar, observe LPEA device working properly.<br><br>Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/acpi/southcluster.asl<br>1 file changed, 23 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/24987/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>index 19a58d1..f7e3168 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/southcluster.asl</span><br><span>@@ -153,6 +153,12 @@</span><br><span>                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,</span><br><span>                              0x00010000,,, FSEG)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+               /* LPEA Memory Region (0x20000000-0x201FFFFF) */</span><br><span style="color: hsl(120, 100%, 40%);">+              DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span style="color: hsl(120, 100%, 40%);">+                         Cacheable, ReadWrite,</span><br><span style="color: hsl(120, 100%, 40%);">+                         0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+                               0x00200000,,, LMEM)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>                /* PCI Memory Region (Top of memory-0xfeafffff) */</span><br><span>           DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,</span><br><span>                                Cacheable, ReadWrite,</span><br><span>@@ -166,6 +172,23 @@</span><br><span>                                 0x00005000,,, TPMR)</span><br><span>  })</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+        /* Update LPEA resource area */</span><br><span style="color: hsl(120, 100%, 40%);">+       CreateDWordField (MCRS, LMEM._MIN, LMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+      CreateDWordField (MCRS, LMEM._MAX, LMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+      CreateDWordField (MCRS, LMEM._LEN, LLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+      If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One)))</span><br><span style="color: hsl(120, 100%, 40%);">+        {</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (LPFW, LMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+            Store (Add (LMIN, 0x001FFFFF), LMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+          Store (0x00200000, LLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+      }</span><br><span style="color: hsl(120, 100%, 40%);">+     Else</span><br><span style="color: hsl(120, 100%, 40%);">+  {</span><br><span style="color: hsl(120, 100%, 40%);">+             Store (Zero, LMIN)</span><br><span style="color: hsl(120, 100%, 40%);">+            Store (Zero, LMAX)</span><br><span style="color: hsl(120, 100%, 40%);">+            Store (Zero, LLEN)</span><br><span style="color: hsl(120, 100%, 40%);">+    }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  /* Update PCI resource area */</span><br><span>       CreateDwordField(MCRS, PMEM._MIN, PMIN)</span><br><span>      CreateDwordField(MCRS, PMEM._MAX, PMAX)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24987">change 24987</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24987"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da </div>
<div style="display:none"> Gerrit-Change-Number: 24987 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>