[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Enable ThunderPeak wifi card

[Roy Mingi Park (Code Review)]

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/24932


Change subject: soc/intel/apollolake: Enable ThunderPeak wifi card
......................................................................

soc/intel/apollolake: Enable ThunderPeak wifi card

This enables ThunderPeak WiFi card on M.2.

TEST=Verify wlan card shows up in lspci

Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c
Signed-off-by: Roy Mingi Park <roy.mingi.park at intel.com>
---
A src/soc/intel/apollolake/acpi/pcie_glk.asl
M src/soc/intel/apollolake/acpi/southbridge.asl
M src/soc/intel/apollolake/chip.c
3 files changed, 131 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/24932/1

diff --git a/src/soc/intel/apollolake/acpi/pcie_glk.asl b/src/soc/intel/apollolake/acpi/pcie_glk.asl
new file mode 100644
index 0000000..32a7d71
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pcie_glk.asl
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (RP02)
+{
+	Name (_ADR, 0x140001)
+	Name (_DDN, "PCIe-B 0")
+	Name (PDST, 0) /* present Detect status */
+
+	/* lowest D-state supported by
+	 * PCIe root port during S0 state
+	 */
+	Name (_S0W, 4)
+
+	/* Dynamic Opregion needed to access registers
+	 * when the controller is in D3 cold
+	 */
+	OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
+	Field (PX01, AnyAcc, NoLock, Preserve)
+	{
+		Offset(0x5A),
+		, 6,
+		PDS, 1,		/* 6, Presence detect Change */
+		Offset(0xE2),	/* RPPGEN - Root Port Power Gating Enable */
+		, 2,
+		L23E, 1,	/* 2, L23_Rdy Entry Request (L23ER) */
+		L23R, 1,	/* 3, L23_Rdy to Detect Transition (L23R2DT) */
+		Offset(0xF4),	/* BLKPLLEN */
+		, 10,
+		BPLL, 1,
+	}
+
+	OperationRegion (PX02, PCI_Config, 0x338, 0x4)
+	Field (PX02, AnyAcc, NoLock, Preserve)
+	{
+		, 26,
+		BDQA, 1		/* BLKDQDA */
+	}
+
+	PowerResource (PXP, 0, 0)
+	{
+		/* Define the PowerResource for PCIe slot */
+		Method (_STA, 0, Serialized)
+		{
+			Store (PDS, PDST)
+			If (LEqual (PDS, 1)) {
+				Return (0xf)
+			} Else {
+				Return (0)
+			}
+		}
+
+		Method (_ON, 0, Serialized)
+		{
+			If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+				/* Enter this condition if device
+				 * is connected
+				 */
+
+				/* De-assert PERST */
+				\_SB.PCI0.PRAS (\PRT0)
+
+				Store (0, BDQA) /* Set BLKDQDA to 0 */
+				Store (0, BPLL) /* Set BLKPLLEN to 0 */
+
+				/* Set L23_Rdy to Detect Transition
+				 * (L23R2DT)
+				 */
+				Store (1, L23R)
+				Sleep (16)
+				Store (0, Local0)
+
+				/* Delay for transition Detect
+				 * and link to train
+				 */
+				While (L23R) {
+					If (Lgreater (Local0, 4)) {
+						Break
+					}
+					Sleep (16)
+					Increment (Local0)
+				}
+			} /* End PDS condition check */
+		}
+
+		Method (_OFF, 0, Serialized)
+		{
+			/* Set L23_Rdy Entry Request (L23ER) */
+			If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+				/* enter this condition if device
+				 * is connected
+				 */
+				Store (1, L23E)
+				Sleep (16)
+				Store (0, Local0)
+				While (L23E) {
+					If (Lgreater (Local0, 4)) {
+						Break
+					}
+					Sleep (16)
+					Increment (Local0)
+				}
+				Store (1, BDQA) /* Set BLKDQDA to 1 */
+				Store (1, BPLL) /* Set BLKPLLEN to 1 */
+
+				/* Assert PERST */
+				\_SB.PCI0.PRDA (\PRT0)
+			} /* End PDS condition check */
+		} /* End of Method_OFF */
+	} /* End PXP */
+
+	Name(_PR0, Package() { PXP })
+	Name(_PR3, Package() { PXP })
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 5b8f9b7..d93234e 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -28,7 +28,11 @@
 }
 
 /* PCIE device */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "pcie_glk.asl"
+#else
 #include "pcie.asl"
+#endif
 
 /* LPSS device */
 #include "lpss.asl"
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 53ffdb9..76e860f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -502,6 +502,7 @@
 	struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
 {
 	silconfig->Gmm = 0;
+	silconfig->PcieRpSelectableDeemphasis[1] = 0;
 }
 
 void __attribute__((weak)) mainboard_devtree_update(struct device *dev)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c
Gerrit-Change-Number: 24932
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park at intel.com>
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