<p>Roy Mingi Park has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24932">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Enable ThunderPeak wifi card<br><br>This enables ThunderPeak WiFi card on M.2.<br><br>TEST=Verify wlan card shows up in lspci<br><br>Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c<br>Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com><br>---<br>A src/soc/intel/apollolake/acpi/pcie_glk.asl<br>M src/soc/intel/apollolake/acpi/southbridge.asl<br>M src/soc/intel/apollolake/chip.c<br>3 files changed, 131 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/24932/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/acpi/pcie_glk.asl b/src/soc/intel/apollolake/acpi/pcie_glk.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..32a7d71</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/acpi/pcie_glk.asl</span><br><span>@@ -0,0 +1,126 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device (RP02)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_ADR, 0x140001)</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_DDN, "PCIe-B 0")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (PDST, 0) /* present Detect status */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* lowest D-state supported by</span><br><span style="color: hsl(120, 100%, 40%);">+ * PCIe root port during S0 state</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_S0W, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dynamic Opregion needed to access registers</span><br><span style="color: hsl(120, 100%, 40%);">+ * when the controller is in D3 cold</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PX01, PCI_Config, 0x00, 0xFF)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PX01, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0x5A),</span><br><span style="color: hsl(120, 100%, 40%);">+ , 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PDS, 1, /* 6, Presence detect Change */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 2,</span><br><span style="color: hsl(120, 100%, 40%);">+ L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */</span><br><span style="color: hsl(120, 100%, 40%);">+ L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset(0xF4), /* BLKPLLEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ , 10,</span><br><span style="color: hsl(120, 100%, 40%);">+ BPLL, 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (PX02, PCI_Config, 0x338, 0x4)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (PX02, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ , 26,</span><br><span style="color: hsl(120, 100%, 40%);">+ BDQA, 1 /* BLKDQDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PowerResource (PXP, 0, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Define the PowerResource for PCIe slot */</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_STA, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PDS, PDST)</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LEqual (PDS, 1)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0xf)</span><br><span style="color: hsl(120, 100%, 40%);">+ } Else {</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_ON, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enter this condition if device</span><br><span style="color: hsl(120, 100%, 40%);">+ * is connected</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* De-assert PERST */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.PRAS (\PRT0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, BDQA) /* Set BLKDQDA to 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, BPLL) /* Set BLKPLLEN to 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set L23_Rdy to Detect Transition</span><br><span style="color: hsl(120, 100%, 40%);">+ * (L23R2DT)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (1, L23R)</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep (16)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Delay for transition Detect</span><br><span style="color: hsl(120, 100%, 40%);">+ * and link to train</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ While (L23R) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (Lgreater (Local0, 4)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Break</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep (16)</span><br><span style="color: hsl(120, 100%, 40%);">+ Increment (Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End PDS condition check */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_OFF, 0, Serialized)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set L23_Rdy Entry Request (L23ER) */</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* enter this condition if device</span><br><span style="color: hsl(120, 100%, 40%);">+ * is connected</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (1, L23E)</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep (16)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ While (L23E) {</span><br><span style="color: hsl(120, 100%, 40%);">+ If (Lgreater (Local0, 4)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Break</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Sleep (16)</span><br><span style="color: hsl(120, 100%, 40%);">+ Increment (Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (1, BDQA) /* Set BLKDQDA to 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (1, BPLL) /* Set BLKPLLEN to 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Assert PERST */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.PRDA (\PRT0)</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End PDS condition check */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End of Method_OFF */</span><br><span style="color: hsl(120, 100%, 40%);">+ } /* End PXP */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_PR0, Package() { PXP })</span><br><span style="color: hsl(120, 100%, 40%);">+ Name(_PR3, Package() { PXP })</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl</span><br><span>index 5b8f9b7..d93234e 100644</span><br><span>--- a/src/soc/intel/apollolake/acpi/southbridge.asl</span><br><span>+++ b/src/soc/intel/apollolake/acpi/southbridge.asl</span><br><span>@@ -28,7 +28,11 @@</span><br><span> }</span><br><span> </span><br><span> /* PCIE device */</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)</span><br><span style="color: hsl(120, 100%, 40%);">+#include "pcie_glk.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> #include "pcie.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> /* LPSS device */</span><br><span> #include "lpss.asl"</span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 53ffdb9..76e860f 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -502,6 +502,7 @@</span><br><span> struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)</span><br><span> {</span><br><span> silconfig->Gmm = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ silconfig->PcieRpSelectableDeemphasis[1] = 0;</span><br><span> }</span><br><span> </span><br><span> void __attribute__((weak)) mainboard_devtree_update(struct device *dev)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24932">change 24932</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24932"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic06b5bfecc5061b53f9256476aeb53bca67c0b9c </div>
<div style="display:none"> Gerrit-Change-Number: 24932 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Roy Mingi Park <roy.mingi.park@intel.com> </div>