[coreboot-gerrit] Change in coreboot[master]: mb/intel/glkrvp: Enable ThunderPeak wifi card

[Roy Mingi Park (Code Review)]

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/24931


Change subject: mb/intel/glkrvp: Enable ThunderPeak wifi card
......................................................................

mb/intel/glkrvp: Enable ThunderPeak wifi card

This enables ThunderPeak WiFi card on M.2.

TEST=Verify wlan card shows up in lspci

Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Signed-off-by: Roy Mingi Park <roy.mingi.park at intel.com>
---
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
2 files changed, 7 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/24931/1

diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 45badcd..d16b88d 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -9,13 +9,13 @@
 	register "pcie_rp1_clkreq_pin" = "3" # wifi/bt
 	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
 	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp4_clkreq_pin" = "1"
+	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
 	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
 
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
 	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_PRT0_UDEF"
+	register "prt0_gpio" = "GPIO_163"
 
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPIO_186"
@@ -123,9 +123,9 @@
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 off end	# - PCIe-A 0 Slot 1
 		device pci 13.1 off end	# - PCIe-A 1
-		device pci 13.2 on  end	# - PCIe-A 2 Onboard Lan
+		device pci 13.2 off end	# - PCIe-A 2 Onboard Lan
 		device pci 13.3 off end	# - PCIe-A 3
-		device pci 14.0 off end # - PCIe-B 0 Slot2
+		device pci 14.0 off  end # - PCIe-B 0 Slot2
 		device pci 14.1 on  end	# - PCIe-B 1 Onboard M2 Slot(Wifi/BT)
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end # - XDCI
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 0646bcf..9737355 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -151,9 +151,9 @@
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/
 	PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/
-	PAD_CFG_NF_IOSSTATE(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ0_B*/
-	PAD_CFG_NF_IOSSTATE(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ1_B*/
-	PAD_CFG_NF_IOSSTATE(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ2_B*/
+	PAD_CFG_GPI(GPIO_120, UP_20K, DEEP),     /* unused */
+	PAD_CFG_GPI(GPIO_121, UP_20K, DEEP),     /* unused */
+	PAD_CFG_GPI(GPIO_122, UP_20K, DEEP),     /* unused */
 	PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/
 	PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/
 	PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Gerrit-Change-Number: 24931
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park at intel.com>
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