<p>Roy Mingi Park has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24931">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/glkrvp: Enable ThunderPeak wifi card<br><br>This enables ThunderPeak WiFi card on M.2.<br><br>TEST=Verify wlan card shows up in lspci<br><br>Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2<br>Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com><br>---<br>M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb<br>M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c<br>2 files changed, 7 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/24931/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>index 45badcd..d16b88d 100644</span><br><span>--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>@@ -9,13 +9,13 @@</span><br><span> register "pcie_rp1_clkreq_pin" = "3" # wifi/bt</span><br><span> register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"</span><br><span> register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(0, 100%, 40%);">- register "pcie_rp4_clkreq_pin" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"</span><br><span> register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"</span><br><span> </span><br><span> # GPIO for PERST_0</span><br><span> # If the Board has PERST_0 signal, assign the GPIO</span><br><span> # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF</span><br><span style="color: hsl(0, 100%, 40%);">- register "prt0_gpio" = "GPIO_PRT0_UDEF"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "prt0_gpio" = "GPIO_163"</span><br><span> </span><br><span> # GPIO for SD card detect</span><br><span> register "sdcard_cd_gpio" = "GPIO_186"</span><br><span>@@ -123,9 +123,9 @@</span><br><span> device pci 12.0 on end # - SATA</span><br><span> device pci 13.0 off end # - PCIe-A 0 Slot 1</span><br><span> device pci 13.1 off end # - PCIe-A 1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 13.2 on end # - PCIe-A 2 Onboard Lan</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.2 off end # - PCIe-A 2 Onboard Lan</span><br><span> device pci 13.3 off end # - PCIe-A 3</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 14.0 off end # - PCIe-B 0 Slot2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 off end # - PCIe-B 0 Slot2</span><br><span> device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT)</span><br><span> device pci 15.0 on end # - XHCI</span><br><span> device pci 15.1 off end # - XDCI</span><br><span>diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>index 0646bcf..9737355 100644</span><br><span>--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c</span><br><span>@@ -151,9 +151,9 @@</span><br><span> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_117, UP_20K, DEEP, NF1),/*PCIE_WAKE1_B*/</span><br><span> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_118, UP_20K, DEEP, NF1),/*PCIE_WAKE2_B*/</span><br><span> PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_119, UP_20K, DEEP, NF1),/*PCIE_WAKE3_B*/</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF_IOSSTATE(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ0_B*/</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF_IOSSTATE(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ1_B*/</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF_IOSSTATE(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ2_B*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* unused */</span><br><span> PAD_CFG_NF_IOSSTATE(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1),/*PCIE_CLKREQ3_B*/</span><br><span> PAD_CFG_NF_IOSSTATE(GPIO_124, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SDA*/</span><br><span> PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24931">change 24931</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 </div>
<div style="display:none"> Gerrit-Change-Number: 24931 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Roy Mingi Park <roy.mingi.park@intel.com> </div>