[coreboot-gerrit] Change in coreboot[master]: sb/intel/common/pmutil: Use new PMBASE API
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Fri Jun 29 10:46:32 CEST 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27287
Change subject: sb/intel/common/pmutil: Use new PMBASE API
......................................................................
sb/intel/common/pmutil: Use new PMBASE API
Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/southbridge/intel/common/pmutil.c
1 file changed, 25 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27287/1
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c
index 03ae473..4e0e357 100644
--- a/src/southbridge/intel/common/pmutil.c
+++ b/src/southbridge/intel/common/pmutil.c
@@ -29,20 +29,18 @@
void alt_gpi_mask(u16 clr, u16 set)
{
- u16 pmbase = get_pmbase();
- u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
+ u16 alt_gp = read_pmbase16(ALT_GP_SMI_EN);
alt_gp &= ~clr;
alt_gp |= set;
- outw(alt_gp, pmbase + ALT_GP_SMI_EN);
+ write_pmbase16(ALT_GP_SMI_EN, alt_gp);
}
void gpe0_mask(u32 clr, u32 set)
{
- u16 pmbase = get_pmbase();
- u32 gpe0 = inl(pmbase + GPE0_EN);
+ u32 gpe0 = read_pmbase32(GPE0_EN);
gpe0 &= ~clr;
gpe0 |= set;
- outl(gpe0, pmbase + GPE0_EN);
+ write_pmbase32(GPE0_EN, gpe0);
}
/**
@@ -51,12 +49,9 @@
*/
u16 reset_pm1_status(void)
{
- u16 pmbase = get_pmbase();
- u16 reg16;
-
- reg16 = inw(pmbase + PM1_STS);
+ u16 reg16 = read_pmbase16(PM1_STS);
/* set status bits are cleared by writing 1 to them */
- outw(reg16, pmbase + PM1_STS);
+ write_pmbase16(PM1_STS, reg16);
return reg16;
}
@@ -73,7 +68,8 @@
if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
printk(BIOS_SPEW, "\n");
- int reg16 = inw(get_pmbase() + PM1_EN);
+
+ int reg16 = read_pmbase16(PM1_EN);
printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
}
@@ -83,12 +79,11 @@
*/
u32 reset_smi_status(void)
{
- u16 pmbase = get_pmbase();
u32 reg32;
- reg32 = inl(pmbase + SMI_STS);
+ reg32 = read_pmbase32(SMI_STS);
/* set status bits are cleared by writing 1 to them */
- outl(reg32, pmbase + SMI_STS);
+ write_pmbase32(SMI_STS, reg32);
return reg32;
}
@@ -125,14 +120,13 @@
*/
u64 reset_gpe0_status(void)
{
- u16 pmbase = get_pmbase();
u32 reg_h, reg_l;
- reg_l = inl(pmbase + GPE0_STS);
- reg_h = inl(pmbase + GPE0_STS + 4);
+ reg_l = read_pmbase32(GPE0_STS);
+ reg_h = read_pmbase32(GPE0_STS + 4);
/* set status bits are cleared by writing 1 to them */
- outl(reg_l, pmbase + GPE0_STS);
- outl(reg_h, pmbase + GPE0_STS + 4);
+ write_pmbase32(GPE0_STS, reg_l);
+ write_pmbase32(GPE0_STS + 4, reg_h);
return (((u64)reg_h) << 32) | reg_l;
}
@@ -169,14 +163,16 @@
*/
u32 reset_tco_status(void)
{
- u32 tcobase = get_pmbase() + 0x60;
u32 reg32;
- reg32 = inl(tcobase + 0x04);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
+ reg32 = read_pmbase32(0x60 + 0x04);
+ /*
+ * set status bits are cleared by writing 1 to them, but don't
+ * clear BOOT_STS before SECOND_TO_STS.
+ */
+ write_pmbase32(0x60 + 0x04, reg32 & ~(1<<18));
if (reg32 & (1 << 18))
- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+ write_pmbase32(0x60 + 0x04, reg32 & (1<<18)); // clear BOOT_STS
return reg32;
}
@@ -206,12 +202,11 @@
*/
void smi_set_eos(void)
{
- u16 pmbase = get_pmbase();
u8 reg8;
- reg8 = inb(pmbase + SMI_EN);
+ reg8 = read_pmbase8(SMI_EN);
reg8 |= EOS;
- outb(reg8, pmbase + SMI_EN);
+ write_pmbase8(SMI_EN, reg8);
}
@@ -231,12 +226,11 @@
*/
u16 reset_alt_gp_smi_status(void)
{
- u16 pmbase = get_pmbase();
u16 reg16;
- reg16 = inl(pmbase + ALT_GP_SMI_STS);
+ reg16 = read_pmbase16(ALT_GP_SMI_STS);
/* set status bits are cleared by writing 1 to them */
- outl(reg16, pmbase + ALT_GP_SMI_STS);
+ write_pmbase16(ALT_GP_SMI_STS, reg16);
return reg16;
}
--
To view, visit https://review.coreboot.org/27287
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963
Gerrit-Change-Number: 27287
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180629/35ac2526/attachment-0001.html>
More information about the coreboot-gerrit
mailing list