[coreboot-gerrit] Change in coreboot[master]: cbfstool: fix FIT entry checksum value for ucode entries

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27266


Change subject: cbfstool: fix FIT entry checksum value for ucode entries
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cbfstool: fix FIT entry checksum value for ucode entries

commit c1072f2 [cbfstool: Update FIT entries in the second bootblock]
incorrectly changed the value of type_checksum_valid for microcode
entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on
Skylake/FSP1.1 devices (and others?).  Correct this by reverting to the
previous value.

Test: build/boot google/chell, observe FspTempRamInit no longer fails,
device boots as expected.

Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M util/cbfstool/fit.c
1 file changed, 1 insertion(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27266/1

diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index 31ab3de..ad9ab37 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -182,8 +182,7 @@
 	 * rather from the MCU header, hence we can assign zero here
 	 */
 	entry->size_reserved = 0x0000;
-	/* Checksum valid should be cleared for MCU */
-	entry->type_checksum_valid = 0;
+	entry->type_checksum_valid = FIT_TYPE_MICROCODE;
 	entry->version = FIT_MICROCODE_VERSION;
 	entry->checksum = 0;
 	fit_entry_add_size(&fit->header, sizeof(struct fit_entry));

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676
Gerrit-Change-Number: 27266
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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