[coreboot-gerrit] Change in coreboot[master]: intel/common/block/scs: Add ability to send early CMD0, CMD1

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25068 )

Change subject: intel/common/block/scs: Add ability to send early CMD0, CMD1
......................................................................


Patch Set 8:

(13 comments)

https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/include/intelblocks/early_mmc.h
File src/soc/intel/common/block/include/intelblocks/early_mmc.h:

https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/include/intelblocks/early_mmc.h@26
PS8, Line 26:  * emmc_rx_cmd_data_cntl1: Rx CMD Data Delay Control 1 (Rx_CMD_Data_dly_1)—Offset 82Ch
line over 80 characters


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/include/intelblocks/early_mmc.h@27
PS8, Line 27:  * emmc_rx_strobe_cntl: Rx Strobe Delay Control (Rx_Strobe_Ctrl_Path)—Offset 830h
line over 80 characters


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/include/intelblocks/early_mmc.h@28
PS8, Line 28:  * emmc_rx_cmd_data_cntl2: Rx CMD Data Path Delay Control 2 (Rx_CMD_Data_dly_2)—Offset 834h
line over 80 characters


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c
File src/soc/intel/common/block/scs/early_mmc.c:

https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@56
PS8, Line 56:         *ctrlr)
code indent should use tabs where possible


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@56
PS8, Line 56:         *ctrlr)
please, no spaces at the start of a line


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@91
PS8, Line 91: 	write32(ioaddr + EMMC_TX_DATA_CNTL1_OFFSET, 
trailing whitespace


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@93
PS8, Line 93: 	write32(ioaddr + EMMC_TX_DATA_CNTL2_OFFSET, 
trailing whitespace


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@95
PS8, Line 95: 	write32(ioaddr + EMMC_RX_CMD_DATA_CNTL1_OFFSET, 
trailing whitespace


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@97
PS8, Line 97: 	write32(ioaddr + EMMC_RX_CMD_DATA_CNTL2_OFFSET, 
trailing whitespace


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@99
PS8, Line 99: 	write32(ioaddr + EMMC_RX_STROBE_CNTL_OFFSET, 
trailing whitespace


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@145
PS8, Line 145: 	mmc_ctrlr = new_mem_sdhci_controller((void*) ioaddr);
"(foo*)" should be "(foo *)"


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@148
PS8, Line 148: 	if (set_mmc_dll((void*) ioaddr) < 0)
that open brace { should be on the previous line


https://review.coreboot.org/#/c/25068/8/src/soc/intel/common/block/scs/early_mmc.c@148
PS8, Line 148: 	if (set_mmc_dll((void*) ioaddr) < 0)
"(foo*)" should be "(foo *)"



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e
Gerrit-Change-Number: 25068
Gerrit-PatchSet: 8
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma at intel.com>
Gerrit-Comment-Date: Thu, 28 Jun 2018 00:40:15 +0000
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