[coreboot-gerrit] Change in coreboot[master]: mb/gigabyte/ga-{h61m-s2pv, b75m-d3h, b75m-d3v}: Clean up mainboard code.
Angel Pons (Code Review)
gerrit at coreboot.org
Sat Jun 23 17:56:55 CEST 2018
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/27211
Change subject: mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code.
......................................................................
mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard code.
I ported ga-h61m-s2pv basing on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.
ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.
Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus at gmail.com>
---
M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
D src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
M src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
M src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
M src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
M src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
M src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
D src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
M src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
M src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
M src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
M src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
M src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
M src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
M src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
M src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
24 files changed, 52 insertions(+), 259 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/27211/1
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
index 580a9ad..8c0f36b 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
@@ -13,7 +13,6 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
- select HAVE_SMI_HANDLER
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
@@ -23,10 +22,6 @@
int
default 25
-config USBDEBUG_HCD_INDEX
- int
- default 2
-
config MAINBOARD_DIR
string
default gigabyte/ga-b75m-d3h
@@ -47,14 +42,6 @@
string
default "pci8086,0162.rom"
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
config IFD_BIOS_SECTION
string
default "0x00600000:0x007fffff"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
deleted file mode 100644
index f87af3c..0000000
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
+++ /dev/null
@@ -1 +0,0 @@
-// Blank
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
index 2d7b43f..5c09059 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -35,8 +35,5 @@
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- // the lid is open by default.
- gnvs->lids = 1;
-
acpi_update_thermal_table(gnvs);
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
index a313f68..6f3cec7 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
@@ -1,7 +1,6 @@
boot_option=Fallback
-debug_level=Spew
+debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-volume=0x3
sata_mode=AHCI
-hyper_threading=Enable
+gfx_uma_size=32M
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
index 7c72c4b..80950cd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
@@ -52,18 +52,15 @@
395 4 e 6 debug_level
#399 1 r 0 unused
-400 8 h 0 volume
-
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 10 r 0 unused
421 1 e 9 sata_mode
-#422 2 r 0 unused
+#422 2 r 0 unused
# coreboot config options: cpu
-424 1 e 2 hyper_threading
#425 7 r 0 unused
# coreboot config options: northbridge
@@ -85,8 +82,6 @@
#ID value text
1 0 Disable
1 1 Enable
-2 0 Enable
-2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
@@ -114,4 +109,4 @@
# -----------------------------------------------------------------
checksums
-checksum 392 415 984
+checksum 392 439 984
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
index 3659354..b0c58f9 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -1,7 +1,7 @@
chip northbridge/intel/sandybridge
# IGD Displays
register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
index c7052d8..665d81b 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -25,16 +25,15 @@
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
- /* global NVS and variables. */
+ /* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
- #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
-
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
index 71d40cb..23cd570 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
@@ -14,8 +14,9 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
+ /* FIXME: Add configuration for sound */
};
-const u32 pc_beep_verbs[0] = {};
+const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
index 90131ff..4e8d9f5 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -15,22 +15,9 @@
* GNU General Public License for more details.
*/
-#include <types.h>
-#include <string.h>
#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <cbfs.h>
static void mainboard_init(struct device *dev)
{
@@ -75,7 +62,9 @@
{
dev->ops->init = mainboard_init;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 5a2c935..6c4fa1e 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -13,30 +13,21 @@
* GNU General Public License for more details.
*/
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
#define SUPERIO_BASE 0x2e
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <superio/ite/it8728f/it8728f.h>
-#include <superio/ite/common/ite.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-
static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
- ite_reg_write(dev, 0xEF, 0x7E); // magic
+ ite_reg_write(dev, 0xEF, 0x7E); // magic SIO disable reboot
ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
@@ -48,7 +39,7 @@
ite_reg_write(dev, 0xe9, 0x27); // bus select disable
ite_reg_write(dev, 0xf0, 0x10); // ?
ite_reg_write(dev, 0xf1, 0x42); // ?
- ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+ ite_reg_write(dev, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
@@ -63,88 +54,13 @@
void mainboard_rcba_config(void)
{
-/*
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
-
- outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
-
- RCBA32(0x3500) = 0x2000035f;
- RCBA32(0x3504) = 0x2000035f;
- RCBA32(0x3508) = 0x2000035f;
- RCBA32(0x350c) = 0x2000035f;
- RCBA32(0x3510) = 0x2000035f;
- RCBA32(0x3514) = 0x2000035f;
- RCBA32(0x3518) = 0x2000035f;
- RCBA32(0x351c) = 0x2000035f;
- RCBA32(0x3520) = 0x2000035f;
- RCBA32(0x3524) = 0x2000035f;
- RCBA32(0x3528) = 0x2000035f;
- RCBA32(0x352c) = 0x2000035f;
- RCBA32(0x3530) = 0x2000035f;
- RCBA32(0x3534) = 0x2000035f;
- RCBA32(0x3560) = 0x024c8001;
- RCBA32(0x3564) = 0x000024a3;
- RCBA32(0x3568) = 0x00040002;
- RCBA32(0x356c) = 0x01000050;
- RCBA32(0x3570) = 0x02000662;
- RCBA32(0x3574) = 0x18000f9f;
- RCBA32(0x3578) = 0x1800ff4f;
- RCBA32(0x357c) = 0x0001d530;
- RCBA32(0x35a0) = 0xc0300c03;
- RCBA32(0x35a4) = 0x00241803;
-
- pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
-
- outw (0x0000, DEFAULT_PMBASE | 0x003c);
-
- RCBA32(0x2240) = 0x00330e71;
- RCBA32(0x2244) = 0x003f0eb1;
- RCBA32(0x2248) = 0x002102cd;
- RCBA32(0x224c) = 0x00f60000;
- RCBA32(0x2250) = 0x00020000;
- RCBA32(0x2254) = 0x00e3004c;
- RCBA32(0x2258) = 0x00e20bef;
- RCBA32(0x2260) = 0x003304ed;
- RCBA32(0x2278) = 0x001107c1;
- RCBA32(0x227c) = 0x001d07e9;
- RCBA32(0x2280) = 0x00e20000;
- RCBA32(0x2284) = 0x00ee0000;
- RCBA32(0x2288) = 0x005b05d3;
- RCBA32(0x2318) = 0x04b8ff2e;
- RCBA32(0x231c) = 0x03930f2e;
-// RCBA32(0x3418) = 0x1fee1fe1;
- RCBA32(0x3808) = 0x005044a3;
- RCBA32(0x3810) = 0x52410000;
- RCBA32(0x3814) = 0x0000008a;
- RCBA32(0x3818) = 0x00000006;
- RCBA32(0x381c) = 0x0000072e;
- RCBA32(0x3820) = 0x0000000a;
- RCBA32(0x3824) = 0x00000123;
- RCBA32(0x3828) = 0x00000009;
- RCBA32(0x382c) = 0x00000001;
- RCBA32(0x3834) = 0x0000061a;
- RCBA32(0x3838) = 0x00000003;
- RCBA32(0x383c) = 0x00000a76;
- RCBA32(0x3840) = 0x00000004;
- RCBA32(0x3844) = 0x0000e5e4;
- RCBA32(0x3848) = 0x0000000e;
-*/
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
void pch_enable_lpc(void)
{
- /*
- * Enable:
- * EC Decode Range PortA30/A20
- * SuperIO Port2E/2F
- * PS/2 Keyboard/Mouse Port60/64
- * FDD Port3F0h-3F5h and Port3F7h
- */
- pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
@@ -181,28 +97,6 @@
read_spd (&spd[3], 0x53, id_only);
}
-#if 0
-static void dmi_config(void)
-{
- DMIBAR32(0x0218) = 0x06aa0b0c;
- DMIBAR32(0x021c) = 0x0b0d0b0d;
- DMIBAR32(0x0300) = 0x0011028d;
- DMIBAR32(0x0304) = 0x002102cd;
- DMIBAR32(0x030c) = 0x007d004b;
- DMIBAR32(0x0310) = 0x007e004c;
- DMIBAR32(0x0318) = 0x002304ad;
- DMIBAR32(0x031c) = 0x003304ed;
- DMIBAR32(0x03b8) = 0x005c05a4;
- DMIBAR32(0x03bc) = 0x006c05e4;
- DMIBAR32(0x0530) = 0x41d3b000;
- DMIBAR32(0x0534) = 0x00019f80;
- DMIBAR32(0x0ba4) = 0x0000000d;
- DMIBAR32(0x0d80) = 0x1c9cfc0b;
- DMIBAR32(0x0e1c) = 0x20000000;
- DMIBAR32(0x0e2c) = 0x20000000;
-}
-#endif
-
void mainboard_early_init(int s3resume) {
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
index b8694f5..2c0bb18 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
@@ -22,10 +22,6 @@
int
default 25
-config USBDEBUG_HCD_INDEX
- int
- default 2
-
config MAINBOARD_DIR
string
default gigabyte/ga-b75m-d3v
@@ -46,14 +42,6 @@
string
default "pci8086,0102.rom"
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
config IFD_BIOS_SECTION
string
default "0x00600000:0x007fffff"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
deleted file mode 100644
index f87af3c..0000000
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
+++ /dev/null
@@ -1 +0,0 @@
-// Blank
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
index 2d7b43f..5c09059 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -35,8 +35,5 @@
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- // the lid is open by default.
- gnvs->lids = 1;
-
acpi_update_thermal_table(gnvs);
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
index a313f68..6f3cec7 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
@@ -1,7 +1,6 @@
boot_option=Fallback
-debug_level=Spew
+debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-volume=0x3
sata_mode=AHCI
-hyper_threading=Enable
+gfx_uma_size=32M
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
index 7c72c4b..80950cd 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
@@ -52,18 +52,15 @@
395 4 e 6 debug_level
#399 1 r 0 unused
-400 8 h 0 volume
-
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 10 r 0 unused
421 1 e 9 sata_mode
-#422 2 r 0 unused
+#422 2 r 0 unused
# coreboot config options: cpu
-424 1 e 2 hyper_threading
#425 7 r 0 unused
# coreboot config options: northbridge
@@ -85,8 +82,6 @@
#ID value text
1 0 Disable
1 1 Enable
-2 0 Enable
-2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
@@ -114,4 +109,4 @@
# -----------------------------------------------------------------
checksums
-checksum 392 415 984
+checksum 392 439 984
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
index 618943c..d7153f4 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
@@ -1,6 +1,6 @@
chip northbridge/intel/sandybridge
register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0 on
chip cpu/intel/socket_LGA1155
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
index c7052d8..665d81b 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -25,16 +25,15 @@
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
- /* global NVS and variables. */
+ /* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
- #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
-
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
index 887eb51..3ae6b5d 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
@@ -36,6 +36,6 @@
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
};
-const u32 pc_beep_verbs[] = {
-};
+const u32 pc_beep_verbs[] = {};
+
AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
index 90131ff..4e8d9f5 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
@@ -15,22 +15,9 @@
* GNU General Public License for more details.
*/
-#include <types.h>
-#include <string.h>
#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <cbfs.h>
static void mainboard_init(struct device *dev)
{
@@ -75,7 +62,9 @@
{
dev->ops->init = mainboard_init;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index a389e68..64c323b 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -13,30 +13,21 @@
* GNU General Public License for more details.
*/
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
#define SUPERIO_BASE 0x2e
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <superio/ite/it8728f/it8728f.h>
-#include <superio/ite/common/ite.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-
static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
- ite_reg_write(dev, 0xEF, 0x7E); // magic
+ ite_reg_write(dev, 0xEF, 0x7E); // magic SIO disable reboot
ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
@@ -48,7 +39,7 @@
ite_reg_write(dev, 0xe9, 0x27); // bus select disable
ite_reg_write(dev, 0xf0, 0x10); // ?
ite_reg_write(dev, 0xf1, 0x42); // ?
- ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+ ite_reg_write(dev, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
@@ -69,14 +60,7 @@
void pch_enable_lpc(void)
{
- /*
- * Enable:
- * EC Decode Range PortA30/A20
- * SuperIO Port2E/2F
- * PS/2 Keyboard/Mouse Port60/64
- * FDD Port3F0h-3F5h and Port3F7h
- */
- pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
@@ -106,6 +90,7 @@
{ 1, 5, 6 },
};
+/* FIXME: This board only has two DIMM slots! */
void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
read_spd (&spd[0], 0x50, id_only);
read_spd (&spd[1], 0x51, id_only);
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
index f53bc06..6e395b3 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
@@ -32,14 +32,6 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
-config HAVE_IFD_BIN
- bool
- default n
-
-config HAVE_ME_BIN
- bool
- default n
-
config MAINBOARD_DIR
string
default "gigabyte/ga-h61m-s2pv"
@@ -68,8 +60,4 @@
int
default 8
-config USBDEBUG_HCD_INDEX # FIXME: check this
- int
- default 2
-
endif # BOARD_GIGABYTE_GA_H61M_S2PV
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
index 9102b82..7ff7fbe 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
@@ -14,14 +14,8 @@
##
chip northbridge/intel/sandybridge
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
- register "gfx.link_frequency_270_mhz" = "0"
register "gfx.ndid" = "3"
- register "gfx.use_spread_spectrum_clock" = "0"
- register "gpu_dp_b_hotplug" = "4"
- register "gpu_dp_c_hotplug" = "4"
- register "gpu_dp_d_hotplug" = "4"
- register "gpu_panel_port_select" = "0"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
device cpu_cluster 0x0 on
chip cpu/intel/socket_LGA1155
device lapic 0x0 on
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
index d5719cc..71d238d 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
@@ -38,9 +38,9 @@
Scope (\_SB) {
Device (PCI0)
{
- #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
- #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index 3e63721..f1cd176 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -57,11 +57,11 @@
void mainboard_config_superio(void)
{
- /* Enable serial port and flip some magic bits */
-
+ /* Enable serial port */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); // magic
+ /* Disable SIO WDT which kicks in DualBIOS */
+ ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
}
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Gerrit-Change-Number: 27211
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus at gmail.com>
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