[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nocturne: Update TSR sensor info

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/27210


Change subject: mb/google/poppy/variants/nocturne: Update TSR sensor info
......................................................................

mb/google/poppy/variants/nocturne: Update TSR sensor info

This patch updates TSR sensor info with appropriate names.
Also, updates Charger effect with correct TSR sensor mapping.

BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board.

Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
1 file changed, 11 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27210/1

diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
index bb42351..fe9f850 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
@@ -18,22 +18,22 @@
 #define DPTF_CPU_CRITICAL		105
 
 #define DPTF_TSR0_SENSOR_ID		1
-#define DPTF_TSR0_SENSOR_NAME		"systherm0"
+#define DPTF_TSR0_SENSOR_NAME		"Ambient"
 #define DPTF_TSR0_PASSIVE		48
 #define DPTF_TSR0_CRITICAL		90
 
 #define DPTF_TSR1_SENSOR_ID		2
-#define DPTF_TSR1_SENSOR_NAME		"systherm1"
+#define DPTF_TSR1_SENSOR_NAME		"Charger"
 #define DPTF_TSR1_PASSIVE		48
 #define DPTF_TSR1_CRITICAL		90
 
 #define DPTF_TSR2_SENSOR_ID		3
-#define DPTF_TSR2_SENSOR_NAME		"systherm2"
+#define DPTF_TSR2_SENSOR_NAME		"DRAM"
 #define DPTF_TSR2_PASSIVE		65
 #define DPTF_TSR2_CRITICAL		75
 
 #define DPTF_TSR3_SENSOR_ID		4
-#define DPTF_TSR3_SENSOR_NAME		"systherm3"
+#define DPTF_TSR3_SENSOR_NAME		"eMMC"
 #define DPTF_TSR3_PASSIVE		65
 #define DPTF_TSR3_CRITICAL		75
 
@@ -52,20 +52,19 @@
 	/* CPU Throttle Effect on CPU */
 	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
 
-	/* CPU Throttle Effect on TSR0 */
+	/* CPU Throttle Effect on Ambient (TSR0) */
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
 
-	/* CPU Throttle Effect on TSR1 */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Throttle Effect on TSR2 */
+	/* CPU Throttle Effect on DRAM (TSR2) */
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 
-	/* CPU Throttle Effect on TSR3 */
+	/* CPU Throttle Effect on eMMC (TSR3) */
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
 
-	/* Charger Throttle Effect on TSR0 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+#ifdef DPTF_ENABLE_CHARGER
+	/* Charger Throttle Effect on Charger (TSR1) */
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+#endif
 })
 
 Name (MPPC, Package ()

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9
Gerrit-Change-Number: 27210
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar at intel.com>
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