<p>Sumeet R Pawnikar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27210">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy/variants/nocturne: Update TSR sensor info<br><br>This patch updates TSR sensor info with appropriate names.<br>Also, updates Charger effect with correct TSR sensor mapping.<br><br>BUG=None<br>BRANCH=None<br>TEST=Build coreboot for Nocturne board.<br><br>Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9<br>Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com><br>---<br>M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl<br>1 file changed, 11 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/27210/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl</span><br><span>index bb42351..fe9f850 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl</span><br><span>+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl</span><br><span>@@ -18,22 +18,22 @@</span><br><span> #define DPTF_CPU_CRITICAL            105</span><br><span> </span><br><span> #define DPTF_TSR0_SENSOR_ID          1</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR0_SENSOR_NAME          "systherm0"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME            "Ambient"</span><br><span> #define DPTF_TSR0_PASSIVE                48</span><br><span> #define DPTF_TSR0_CRITICAL                90</span><br><span> </span><br><span> #define DPTF_TSR1_SENSOR_ID           2</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR1_SENSOR_NAME          "systherm1"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME            "Charger"</span><br><span> #define DPTF_TSR1_PASSIVE                48</span><br><span> #define DPTF_TSR1_CRITICAL                90</span><br><span> </span><br><span> #define DPTF_TSR2_SENSOR_ID           3</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR2_SENSOR_NAME          "systherm2"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_NAME            "DRAM"</span><br><span> #define DPTF_TSR2_PASSIVE           65</span><br><span> #define DPTF_TSR2_CRITICAL                75</span><br><span> </span><br><span> #define DPTF_TSR3_SENSOR_ID           4</span><br><span style="color: hsl(0, 100%, 40%);">-#define DPTF_TSR3_SENSOR_NAME          "systherm3"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_SENSOR_NAME            "eMMC"</span><br><span> #define DPTF_TSR3_PASSIVE           65</span><br><span> #define DPTF_TSR3_CRITICAL                75</span><br><span> </span><br><span>@@ -52,20 +52,19 @@</span><br><span>         /* CPU Throttle Effect on CPU */</span><br><span>     Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* CPU Throttle Effect on TSR0 */</span><br><span style="color: hsl(120, 100%, 40%);">+     /* CPU Throttle Effect on Ambient (TSR0) */</span><br><span>  Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        /* CPU Throttle Effect on TSR1 */</span><br><span style="color: hsl(0, 100%, 40%);">-       Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-    /* CPU Throttle Effect on TSR2 */</span><br><span style="color: hsl(120, 100%, 40%);">+     /* CPU Throttle Effect on DRAM (TSR2) */</span><br><span>     Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        /* CPU Throttle Effect on TSR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+     /* CPU Throttle Effect on eMMC (TSR3) */</span><br><span>     Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-        /* Charger Throttle Effect on TSR0 */</span><br><span style="color: hsl(0, 100%, 40%);">-   Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+      /* Charger Throttle Effect on Charger (TSR1) */</span><br><span style="color: hsl(120, 100%, 40%);">+       Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> })</span><br><span> </span><br><span> Name (MPPC, Package ()</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27210">change 27210</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27210"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9 </div>
<div style="display:none"> Gerrit-Change-Number: 27210 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> </div>