[coreboot-gerrit] Change in coreboot[master]: google/octopus: Update Phaser's GPIO table
Nick Chen (Code Review)
gerrit at coreboot.org
Wed Jun 20 11:45:42 CEST 2018
Nick Chen has uploaded this change for review. ( https://review.coreboot.org/27171
Change subject: google/octopus: Update Phaser's GPIO table
......................................................................
google/octopus: Update Phaser's GPIO table
Update GPIO settings to meet phaser's schematic design.
BRANCH=master
BUG=none
TEST=emerge-octopus coreboot
Change-Id: If5777a98d21df7a30503ada24c7000994aa4c3de
Signed-off-by: nickchen <nickchen at ami.corp-partner.google.com>
---
A src/mainboard/google/octopus/variants/phaser/Makefile.inc
A src/mainboard/google/octopus/variants/phaser/gpio.c
2 files changed, 339 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27171/1
diff --git a/src/mainboard/google/octopus/variants/phaser/Makefile.inc b/src/mainboard/google/octopus/variants/phaser/Makefile.inc
new file mode 100644
index 0000000..7c092e4
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phaser/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c
new file mode 100644
index 0000000..a2b0273
--- /dev/null
+++ b/src/mainboard/google/octopus/variants/phaser/gpio.c
@@ -0,0 +1,334 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+#include <compiler.h>
+
+/*
+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
+ * table found in EDS vol 1, but some pins aren't grouped functionally in
+ * the table so those were moved for more logical grouping.
+ */
+static const struct pad_config gpio_table[] = {
+ /* NORTHWEST COMMUNITY GPIOS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TP_GPIO5 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK0 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_0 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_1 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_3 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_4 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_5 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_6 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_7*/
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */
+ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNVI_MFUART2_RXD_PTI_11 */
+ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNVI_MFUART2_TXD_PTI_12 */
+ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNVI_GNSS_PA_BLANKING_PTI_13 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_14 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_15 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_CLK2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_16 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_17 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_18 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_19 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_20 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_21 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_22 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_23 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_CLK_PTICLK3 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_DATA_PTITRACE3_0 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_1 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_3 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_4 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_5 */
+ PAD_CFG_GPIO_HI_Z(GPIO_42, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_WIFI_RST_N -- TP135 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_A_OC_ODL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_C_OC_ODL */
+ PAD_CFG_GPIO_HI_Z(GPIO_46, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO46 -- TP37 */
+ PAD_CFG_GPIO_HI_Z(GPIO_47, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO47 -- TP31 */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SDA */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SCL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */
+ PAD_CFG_GPIO_HI_Z(GPIO_52, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SDA */
+ PAD_CFG_GPIO_HI_Z(GPIO_53, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SCL */
+ PAD_CFG_GPIO_HI_Z(GPIO_54, NONE, DEEP, HIZCRx0, DISPUPD), /* TP78 */
+ PAD_CFG_GPIO_HI_Z(GPIO_55, NONE, DEEP, HIZCRx0, DISPUPD), /* TP77 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SDA */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SCL */
+ PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SDA */
+ PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SCL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_MIPI60TX_UART */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHTX_MIPI60RX_UART */
+ PAD_NC(GPIO_62, NONE), /* TP48 */
+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_UART2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* PCHTX_UART2 */
+ PAD_CFG_GPIO_HI_Z(GPIO_66, NONE, DEEP, HIZCRx0, DISPUPD), /* TP1 */
+ PAD_CFG_GPIO_HI_Z(GPIO_67, NONE, DEEP, HIZCRx0, DISPUPD), /* EN_PP3300_DX_LTE_SOC -- TP45 */
+ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
+ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
+ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */
+ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */
+ PAD_NC(GPIO_72, NONE), /* TP_AP_PMC_SPI_TX -- NC */
+ PAD_NC(GPIO_73, NONE), /* TP_AP_PMC_SPI_CLK -- NC */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCH_PROCHOT_ODL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_ODL */
+ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* TOUCHSCREEN_INT_ODL */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPIO_HI_Z(GPIO_214, NONE, DEEP, HIZCRx0, DISPUPD), /* P_SENSOR_INT_L -- TP69 */
+
+ /* NORTH COMMUNITY GPIOS */
+
+ /* svid - unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_76 */
+ PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_77 */
+ PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_78 */
+
+ /* LPSS */
+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */
+ PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */
+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
+ PAD_NC(GPIO_84, NONE), /* TP73 */
+ PAD_NC(GPIO_85, NONE), /* TP63 */
+ PAD_NC(GPIO_86, NONE), /* TP47 */
+ PAD_NC(GPIO_87, NONE), /* TP_PCH_GPIO_87_PD -- TP36 */
+ PAD_NC(GPIO_88, NONE), /* TP62 */
+ PAD_NC(GPIO_89, NONE), /* TP50 */
+
+ /* Fast SPI */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCH_SPI_CS0_L */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MOSI */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MISO_R */
+ PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* PCH_SPI_CLK */
+
+ /* PMU Signals */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PLT_RST_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* EC_PCH_PWR_BTN_ODL */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PCH_SLP_S0_L */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PCH_SLP_S3_L */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PCH_SLP_S4_L */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */
+ PAD_CFG_GPIO_HI_Z(GPIO_104, NONE, DEEP, HIZCRx0, DISPUPD),/* EN_PP3300_EMMC -- TP30 */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* TOUCHSCREEN_RST */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* SYS_RST_ODL */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/* PCH_SUSCLK */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */
+
+ /* I2C5 - Audio */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SDA_Q */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SCL_Q */
+
+ /* I2C6 - Trackpad */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SDA */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SCL */
+
+ /* I2C7 - Touchscreen */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SDA */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SCL */
+
+ /* PCIE_WAKE[0:3]_B */
+ PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
+ PAD_CFG_GPIO_HI_Z(GPIO_117, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_WAKE_L -- TP80 */
+ PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* TP164 */
+ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* WLAN_PCIE_WAKE_ODL */
+
+ /* PCIE_CLKREQ[0:3]_B */
+ PAD_CFG_GPIO_HI_Z(GPIO_120, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ0_ODL -- TP157 */
+ PAD_CFG_GPIO_HI_Z(GPIO_121, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ1_ODL -- TP145 */
+ PAD_CFG_GPIO_HI_Z(GPIO_122, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ2_ODL -- TP171 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* WLAN_PCIE_CLKREQ_ODL */
+
+ /* DDI[0:1] SDA and SCL -- unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */
+ PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */
+
+ /* Panel 0 control */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* EN_PP3300_EDP_DX */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTEN */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTCTL_1V8 */
+
+ /* Hot plug detect. */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C0_HPD_1V8_ODL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C1_HPD_1V8_ODL */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* EDP_HPD_PANEL_1V8_ODL */
+
+ PAD_NC(GPIO_134, NONE),/* TP96 */
+ PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
+ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */
+ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */
+ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_INT_ODL */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */
+ // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others).
+ // Settings here do not match table
+ // Also we may be able to use eSPI WAKE# Virtual Wire instead
+ PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */
+ PAD_CFG_GPIO_HI_Z(GPIO_143, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_SAR_ODL -- TP64 */
+ PAD_CFG_GPIO_HI_Z(GPIO_144, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_144 -- TP49 */
+ PAD_CFG_GPIO_HI_Z(GPIO_145, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_145 -- TP7 */
+ PAD_CFG_GPIO_HI_Z(GPIO_146, NONE, DEEP, HIZCRx0, DISPUPD),/* TP94 */
+
+ /*
+ * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for
+ * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO
+ * and kept unconnected to allow S0ix entry.
+ */
+
+ /* AUDIO COMMUNITY GPIOS*/
+ PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD), /* TP70 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SCLK_R -- TP53 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SFRM_R -- TP54 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_PCH_RX -- TP57 */
+ PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD), /* I2S0_PCH_TX -- TP59 */
+ PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD), /* LTE_OFF_ODL -- TP65 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SCLK_SPKR */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SFRM_SPKR */
+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_PCH_TX_SPKR_RX */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* I2S2_SCLK_R */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_SFRM_R */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_RX */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_TX */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_MCLK_R */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1_R */
+ PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_B1 -- DMIC_CLK2_R */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA_R */
+ PAD_CFG_GPIO_HI_Z(GPIO_174, NONE, DEEP, HIZCRx0, DISPUPD), /* AVS_M_CLK_AB2 -- TP_GPIO_174 */
+ PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 -- DMIC_CAM2_DATA */
+
+ /* SCC COMMUNITY GPIOS */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* TP_SMB_ALERT_N */
+ PAD_CFG_GPIO_HI_Z(GPIO_177, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_SMB_CLK -- TP160 */
+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* EC_IN_RW_OD */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNVI_BRI_DT_R */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNVI_BRI_RSP */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNVI_RGI_DT_R */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNVI_RF_RESET_L */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_CLK */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT0 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT1 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT2 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT3 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT4 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT5 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT6 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT7 */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_CMD */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_RCLK */
+ PAD_CFG_GPIO_HI_Z(GPIO_210, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_GPIO210 */
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
+ /* GSPI0_INT */
+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
+ DISPUPD), /* H1_PCH_INT_ODL */
+ /* GSPI0_CLK */
+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
+ /* GSPI0_CS# */
+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */
+ /* GSPI0_MISO */
+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
+ /* GSPI0_MOSI */
+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
+
+ /* Enable power to wifi early in bootblock and de-assert PERST#. */
+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
+
+ /*
+ * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak
+ * pull-up for proper operation. Since there is no external pull present
+ * on this platform, configure an internal weak pull-up.
+ */
+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1,
+ ENPU), /* ESPI_IO1 */
+};
+
+const struct pad_config *__weak
+variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* GPIO settings before entering sleep. */
+static const struct pad_config sleep_gpio_table[] = {
+};
+
+/* GPIO settings before entering slp_s5. */
+static const struct pad_config sleep_s5_gpio_table[] = {
+ /* BT_DISABLE_L */
+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RXDCRx1, SAME),
+};
+
+const struct pad_config *__weak
+variant_sleep_gpio_table(size_t *num, int slp_typ)
+{
+ if (slp_typ == ACPI_S5) {
+ *num = ARRAY_SIZE(sleep_s5_gpio_table);
+ return sleep_s5_gpio_table;
+ }
+
+ *num = ARRAY_SIZE(sleep_gpio_table);
+ return sleep_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If5777a98d21df7a30503ada24c7000994aa4c3de
Gerrit-Change-Number: 27171
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Chen <nickchen at ami.corp-partner.google.com>
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