<p>Nick Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27171">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/octopus: Update Phaser's GPIO table<br><br>Update GPIO settings to meet phaser's schematic design.<br><br>BRANCH=master<br>BUG=none<br>TEST=emerge-octopus coreboot<br><br>Change-Id: If5777a98d21df7a30503ada24c7000994aa4c3de<br>Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com><br>---<br>A src/mainboard/google/octopus/variants/phaser/Makefile.inc<br>A src/mainboard/google/octopus/variants/phaser/gpio.c<br>2 files changed, 339 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27171/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/phaser/Makefile.inc b/src/mainboard/google/octopus/variants/phaser/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7c092e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/phaser/Makefile.inc</span><br><span>@@ -0,0 +1,5 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += gpio.c</span><br><span>diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a2b0273</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/octopus/variants/phaser/gpio.c</span><br><span>@@ -0,0 +1,334 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'</span><br><span style="color: hsl(120, 100%, 40%);">+ * table found in EDS vol 1, but some pins aren't grouped functionally in</span><br><span style="color: hsl(120, 100%, 40%);">+ * the table so those were moved for more logical grouping.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NORTHWEST COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TP_GPIO5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_7*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNVI_MFUART2_RXD_PTI_11 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNVI_MFUART2_TXD_PTI_12 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNVI_GNSS_PA_BLANKING_PTI_13 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_14 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_15 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_CLK2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_16 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_17 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_18 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_19 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_20 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_21 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_22 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_CLK_PTICLK3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DCI_DATA_PTITRACE3_0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DGB_PTI_DATA_TRACE3_5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_42, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_WIFI_RST_N -- TP135 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_A_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_C_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_46, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO46 -- TP37 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_47, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_GPIO47 -- TP31 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PCH_PMIC_I2C_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_52, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_53, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_P_SENSOR_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_54, NONE, DEEP, HIZCRx0, DISPUPD), /* TP78 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_55, NONE, DEEP, HIZCRx0, DISPUPD), /* TP77 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* DBG_PCH_I2C_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* PCH_I2C_H1_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_MIPI60TX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHTX_MIPI60RX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_62, NONE), /* TP48 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* PCHRX_UART2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* PCHTX_UART2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_66, NONE, DEEP, HIZCRx0, DISPUPD), /* TP1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_67, NONE, DEEP, HIZCRx0, DISPUPD), /* EN_PP3300_DX_LTE_SOC -- TP45 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_72, NONE), /* TP_AP_PMC_SPI_TX -- NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_73, NONE), /* TP_AP_PMC_SPI_CLK -- NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCH_PROCHOT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* TOUCHSCREEN_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_214, NONE, DEEP, HIZCRx0, DISPUPD), /* P_SENSOR_INT_L -- TP69 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NORTH COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* svid - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_76 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_77 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_PCH_GPIO_78 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* LPSS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_84, NONE), /* TP73 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_85, NONE), /* TP63 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_86, NONE), /* TP47 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_87, NONE), /* TP_PCH_GPIO_87_PD -- TP36 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_88, NONE), /* TP62 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_89, NONE), /* TP50 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Fast SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCH_SPI_CS0_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_SPI_MISO_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* PCH_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMU Signals */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PLT_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* EC_PCH_PWR_BTN_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PCH_SLP_S0_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PCH_SLP_S3_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PCH_SLP_S4_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_104, NONE, DEEP, HIZCRx0, DISPUPD),/* EN_PP3300_EMMC -- TP30 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* TOUCHSCREEN_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* SYS_RST_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/* PCH_SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C5 - Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SDA_Q */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_AUDIO_SCL_Q */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C6 - Trackpad */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TRACKPAD_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* I2C7 - Touchscreen */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PCH_I2C_TOUCHSCREEN_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIE_WAKE[0:3]_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_117, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_WAKE_L -- TP80 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* TP164 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* WLAN_PCIE_WAKE_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PCIE_CLKREQ[0:3]_B */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_120, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ0_ODL -- TP157 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_121, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ1_ODL -- TP145 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_122, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_CLKREQ2_ODL -- TP171 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* WLAN_PCIE_CLKREQ_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DDI[0:1] SDA and SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Panel 0 control */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* EN_PP3300_EDP_DX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* SOC_EDP_BKLTCTL_1V8 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hot plug detect. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C0_HPD_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* USB_C1_HPD_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* EDP_HPD_PANEL_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_NC(GPIO_134, NONE),/* TP96 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others).</span><br><span style="color: hsl(120, 100%, 40%);">+ // Settings here do not match table</span><br><span style="color: hsl(120, 100%, 40%);">+ // Also we may be able to use eSPI WAKE# Virtual Wire instead</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_143, NONE, DEEP, HIZCRx0, DISPUPD),/* LTE_SAR_ODL -- TP64 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_144, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_144 -- TP49 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_145, NONE, DEEP, HIZCRx0, DISPUPD),/* TP_GPIO_145 -- TP7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_146, NONE, DEEP, HIZCRx0, DISPUPD),/* TP94 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for</span><br><span style="color: hsl(120, 100%, 40%);">+ * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ * and kept unconnected to allow S0ix entry.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* AUDIO COMMUNITY GPIOS*/</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD), /* TP70 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SCLK_R -- TP53 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_SFRM_R -- TP54 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S0_PCH_RX -- TP57 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD), /* I2S0_PCH_TX -- TP59 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD), /* LTE_OFF_ODL -- TP65 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SCLK_SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_SFRM_SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* I2S_PCH_TX_SPKR_RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* I2S2_SCLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_SFRM_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_RX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_PCH_TX */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* I2S2_MCLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_B1 -- DMIC_CLK2_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_174, NONE, DEEP, HIZCRx0, DISPUPD), /* AVS_M_CLK_AB2 -- TP_GPIO_174 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 -- DMIC_CAM2_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SCC COMMUNITY GPIOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* TP_SMB_ALERT_N */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_177, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_PCH_SMB_CLK -- TP160 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* EC_IN_RW_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNVI_BRI_DT_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNVI_BRI_RSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNVI_RGI_DT_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNVI_RF_RESET_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_DAT7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPIO_HI_Z(GPIO_210, NONE, DEEP, HIZCRx0, DISPUPD), /* TP_GPIO210 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__weak variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIOs needed prior to ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DISPUPD), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GSPI0_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable power to wifi early in bootblock and de-assert PERST#. */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak</span><br><span style="color: hsl(120, 100%, 40%);">+ * pull-up for proper operation. Since there is no external pull present</span><br><span style="color: hsl(120, 100%, 40%);">+ * on this platform, configure an internal weak pull-up.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1,</span><br><span style="color: hsl(120, 100%, 40%);">+ ENPU), /* ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__weak</span><br><span style="color: hsl(120, 100%, 40%);">+variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO settings before entering sleep. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config sleep_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPIO settings before entering slp_s5. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config sleep_s5_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* BT_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RXDCRx1, SAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *__weak</span><br><span style="color: hsl(120, 100%, 40%);">+variant_sleep_gpio_table(size_t *num, int slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (slp_typ == ACPI_S5) {</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(sleep_s5_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return sleep_s5_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(sleep_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return sleep_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27171">change 27171</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27171"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If5777a98d21df7a30503ada24c7000994aa4c3de </div>
<div style="display:none"> Gerrit-Change-Number: 27171 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Chen <nickchen@ami.corp-partner.google.com> </div>