[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27140


Change subject: soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion
......................................................................

soc/intel/baytrail: Fix Kconfig for mrc.bin inclusion

Is used the sandybridge systemagent binary and mentioned that in the
help text which is simply wrong and won't work.

This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by
default.

Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/soc/intel/baytrail/Kconfig
1 file changed, 8 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27140/1

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 1f7e21e..b4dc823 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -67,22 +67,20 @@
 	default 0x100000
 
 config HAVE_MRC
-	bool "Add a Memory Reference Code binary"
-	default y
+	bool "Add a System Agent binary"
 	help
-	  Select this option to add a blob containing
-	  memory reference code.
+	  Select this option to add a System Agent binary to
+	  the resulting coreboot image.
+
 	  Note: Without this binary coreboot will not work
 
-if HAVE_MRC
-
 config MRC_FILE
-	string "Intel memory refeference code path and filename"
-	default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
+	string "Intel System Agent path and filename"
+	depends on HAVE_MRC
+	default "mrc.bin"
 	help
 	  The path and filename of the file to use as System Agent
-	  binary. Note that this points to the sandybridge binary file
-	  which is will not work, but it serves its purpose to do builds.
+	  binary.
 
 config MRC_BIN_ADDRESS
 	hex
@@ -92,8 +90,6 @@
 	bool "Enable MRC RMT training + debug prints"
 	default n
 
-endif # HAVE_MRC
-
 # Cache As RAM region layout:
 #
 # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e
Gerrit-Change-Number: 27140
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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