[coreboot-gerrit] Change in coreboot[master]: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly ca...
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Jun 16 21:50:08 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27134
Change subject: [TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached
......................................................................
[TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached
Test if a large region is properly cached to see if L2 cache is
properly working.
Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
M src/cpu/intel/socket_LGA775/Kconfig
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27134/1
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index cd55ad4..27afcf5 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -109,6 +109,8 @@
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
+ movl $MTRR_PHYS_MASK(2), %ecx
+ wrmsr
movl $LAPIC_BASE_MSR, %ecx
not %edx
movl %edx, %ebx
@@ -251,6 +253,18 @@
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
+ /* Set Cache-as-RAM base address. */
+ movl $(MTRR_PHYS_BASE(2)), %ecx
+ movl $(CONFIG_TEST_DCACHE_BASE | MTRR_TYPE_WRBACK), %eax
+ xorl %edx, %edx
+ wrmsr
+
+ /* Set Cache-as-RAM mask. */
+ movl $(MTRR_PHYS_MASK(2)), %ecx
+ rdmsr
+ movl $(~(CONFIG_TEST_DCACHE_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+ wrmsr
+
post_code(0x2b)
/* Enable MTRR. */
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index c36e046..727e298 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -12,11 +12,13 @@
*/
#include <arch/cpu.h>
+#include <arch/io.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <arch/symbols.h>
#include <program_loading.h>
+#include <halt.h>
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
@@ -42,6 +44,13 @@
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
+ for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4)
+ write32((u8 *)CONFIG_TEST_DCACHE_BASE + i, 0x5bb54aa4);
+
+ for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4)
+ if (read32((u8 *)CONFIG_TEST_DCACHE_BASE + i) != 0x5bb54aa4)
+ halt();
+
mainboard_romstage_entry(bist);
/* Check the stack. */
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..f7946b3 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -23,4 +23,12 @@
hex
default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+config TEST_DCACHE_SIZE
+ hex
+ default 0x40000 # 256kB
+
+config TEST_DCACHE_BASE
+ hex
+ default 0x1400000 # 20MB
+
endif # CPU_INTEL_SOCKET_LGA775
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a
Gerrit-Change-Number: 27134
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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