<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27134">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[TEST]cpu/intel/p4-netburst/CAR: Test if a huge region is properly cached<br><br>Test if a large region is properly cached to see if L2 cache is<br>properly working.<br><br>Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/p4-netburst/cache_as_ram.S<br>M src/cpu/intel/car/romstage.c<br>M src/cpu/intel/socket_LGA775/Kconfig<br>3 files changed, 31 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27134/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S</span><br><span>index cd55ad4..27afcf5 100644</span><br><span>--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S</span><br><span>+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S</span><br><span>@@ -109,6 +109,8 @@</span><br><span> wrmsr</span><br><span> movl $MTRR_PHYS_MASK(1), %ecx</span><br><span> wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_PHYS_MASK(2), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span> movl $LAPIC_BASE_MSR, %ecx</span><br><span> not %edx</span><br><span> movl %edx, %ebx</span><br><span>@@ -251,6 +253,18 @@</span><br><span> movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span> wrmsr</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_BASE(2)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(CONFIG_TEST_DCACHE_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ xorl %edx, %edx</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(MTRR_PHYS_MASK(2)), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(~(CONFIG_TEST_DCACHE_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> post_code(0x2b)</span><br><span> </span><br><span> /* Enable MTRR. */</span><br><span>diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c</span><br><span>index c36e046..727e298 100644</span><br><span>--- a/src/cpu/intel/car/romstage.c</span><br><span>+++ b/src/cpu/intel/car/romstage.c</span><br><span>@@ -12,11 +12,13 @@</span><br><span> */</span><br><span> </span><br><span> #include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <cpu/intel/romstage.h></span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <arch/symbols.h></span><br><span> #include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <halt.h></span><br><span> </span><br><span> #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000</span><br><span> </span><br><span>@@ -42,6 +44,13 @@</span><br><span> for (i = 0; i < num_guards; i++)</span><br><span> stack_base[i] = stack_guard;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((u8 *)CONFIG_TEST_DCACHE_BASE + i, 0x5bb54aa4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < CONFIG_TEST_DCACHE_SIZE; i = i + 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (read32((u8 *)CONFIG_TEST_DCACHE_BASE + i) != 0x5bb54aa4)</span><br><span style="color: hsl(120, 100%, 40%);">+ halt();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> mainboard_romstage_entry(bist);</span><br><span> </span><br><span> /* Check the stack. */</span><br><span>diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig</span><br><span>index 8b227bd..f7946b3 100644</span><br><span>--- a/src/cpu/intel/socket_LGA775/Kconfig</span><br><span>+++ b/src/cpu/intel/socket_LGA775/Kconfig</span><br><span>@@ -23,4 +23,12 @@</span><br><span> hex</span><br><span> default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config TEST_DCACHE_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x40000 # 256kB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config TEST_DCACHE_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1400000 # 20MB</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # CPU_INTEL_SOCKET_LGA775</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27134">change 27134</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibef20c86d4377ed36ef8ad1bcff5e1eb5c9b766a </div>
<div style="display:none"> Gerrit-Change-Number: 27134 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>