[coreboot-gerrit] Change in coreboot[master]: src/sb: Fix non-local header treated as local

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27130


Change subject: src/sb: Fix non-local header treated as local
......................................................................

src/sb: Fix non-local header treated as local

Change-Id: I4b9bcb74b6441db9e44fe471b9cd789e42e7093a
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/ibexpeak/smihandler.c
4 files changed, 4 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27130/1

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 427e58c..498480a 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <string.h>
 #include <arch/io.h>
 #include <cbmem.h>
@@ -27,7 +26,7 @@
 #include <southbridge/intel/common/rcba.h>
 #include "pch.h"
 /* For DMI bar.  */
-#include "northbridge/intel/sandybridge/sandybridge.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
 
 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
 
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 9ce9dc9..9673f28 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -18,7 +18,7 @@
 #include <stdint.h>
 #include "pch.h"
 #include <southbridge/intel/common/rcba.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
 
 void
 southbridge_configure_default_intmap(void)
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index a036858..8df4a00 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -15,10 +15,9 @@
  */
 
 #include <arch/io.h>
-#include <console/console.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
-#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE.  */
+#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE.  */
 #include "pch.h"
 
 void
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 12a7ac0..d920ef7 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -32,7 +32,7 @@
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include "northbridge/intel/nehalem/nehalem.h"
+#include <northbridge/intel/nehalem/nehalem.h>
 #include <southbridge/intel/common/gpio.h>
 #include <arch/io.h>
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4b9bcb74b6441db9e44fe471b9cd789e42e7093a
Gerrit-Change-Number: 27130
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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